Browse Prior Art Database

Overlapped Clock Mechanism to Reset Control Signal

IP.com Disclosure Number: IPCOM000039519D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Lusch, RF: AUTHOR [+2]

Abstract

The use of branches in a pipelined system causes many problems with synchronizing instructions and also causes degradations in performance. The reason for this is because by the time a branch is detected by the processor, the instruction pipeline unit has already started to fetch the next instruction. Generally this would not cause much of a delay unless fetching the next instruction is complicated for some reason, such as requiring a main storage access. Because accessing main storage is typically very slow compared to instruction execution, and the instruction being fetched is not going to be used because of the branch, performance is affected. Even if the storage operation could be canceled after it has started, it would still be necessary to re- synchronize before fetching the target of the branch.

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Overlapped Clock Mechanism to Reset Control Signal

The use of branches in a pipelined system causes many problems with synchronizing instructions and also causes degradations in performance. The reason for this is because by the time a branch is detected by the processor, the instruction pipeline unit has already started to fetch the next instruction. Generally this would not cause much of a delay unless fetching the next instruction is complicated for some reason, such as requiring a main storage access. Because accessing main storage is typically very slow compared to instruction execution, and the instruction being fetched is not going to be used because of the branch, performance is affected. Even if the storage operation could be canceled after it has started, it would still be necessary to re- synchronize before fetching the target of the branch. This would require at least one cycle due to the complexity of several control signals involved. This situation is prevented and processor performance is significantly enhanced as follows. The circuit involved consists mainly of two polarity-hold latches. The first of these latches must have two separate data ports, each with its own clock. It is known as a double-clocked latch L1 (Fig. 1). The purpose of L1 is to detect an extended operation, such as a memory access, that will be required to fetch the next sequential instruction. It is generated as soon as the situation is known. Latch L2 is generated or gated by L1, as seen in Fig. 1. It is shown as being a single latch, but it is more likely to be a sequence of latches used to handle the memory operation. An example would be one of the controls used for determining priority if memory can be accessed by more than one unit. As seen in the timing diagram in Fig. 2, the normal instruction fetch and execution for a typical pipelined processor using this principle is found in lines 1 and 2. The first instruction is fetched in...