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Primary Error Detection System for I/O Apparatus

IP.com Disclosure Number: IPCOM000039523D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Bell, BC: AUTHOR [+3]

Abstract

In a distributed processor control unit architecture for line printers and other I/O machines, a main processor supervises separate controls or controllers provided for each of the different sectors of the machines, e.g., paper feed carriage, type band drive, and hammer firing logic circuitry. In such an environment, error detection and follow-on problem determination and resolution is complicated. The solution is provided by circuitry which detects and identifies the first or primary error and blocks interference from secondary errors. As shown in the figure, an Error Set signal from the error detection logic 10 of a machine sector sets an appropriate latch 11 of error register 12.

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Primary Error Detection System for I/O Apparatus

In a distributed processor control unit architecture for line printers and other I/O machines, a main processor supervises separate controls or controllers provided for each of the different sectors of the machines, e.g., paper feed carriage, type band drive, and hammer firing logic circuitry. In such an environment, error detection and follow-on problem determination and resolution is complicated. The solution is provided by circuitry which detects and identifies the first or primary error and blocks interference from secondary errors. As shown in the figure, an Error Set signal from the error detection logic 10 of a machine sector sets an appropriate latch 11 of error register 12. An Any Error signal from OR circuit 13, in response to the setting of any of latches 11, is gated through AND circuit 14, resulting in an Error Interrupt (Irpt) signal to the main processor on line
15. The Any Error signal from OR circuit 13 is sent to Inverter circuit 16 which degates AND circuits 17, thereby blocking secondary errors produced by error detection logic 10 from setting other latches 11 of error register 12. The Any Error signal also applies to the D input of flip flop (FF) 18. An Error Read Command (Cmd) signal from the main processor on line 19 gates the error information in register 12 through AND circuits 20 onto bit lines 21 of a data bus connection to the main processor. The trailing edge of the Error Read Cmd signa...