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CMOS Exclusive or (Xor) Using Minimum Number of Devices

IP.com Disclosure Number: IPCOM000039530D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Griffith, D: AUTHOR [+3]

Abstract

The Exclusive OR (XOR) is an important logic circuit in machine architecture and is frequently used in applications, such as parity generators. The CMOS (complementary metal oxide semiconductor) circuit disclosed in this article uses a small number of field-effect transistors (FETs), four P-type and three N-type, to produce the XOR function. The CMOS XOR circuit design shown utilizes seven FET transistors to obtain a high physical chip density and a minimum delay. It operates as follows: When both inputs A and B are at an up level, transistors Q2 and Q5 are on, and output node C goes to the up level through the conduction of transistor Q5 to the up level at input node A.

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CMOS Exclusive or (Xor) Using Minimum Number of Devices

The Exclusive OR (XOR) is an important logic circuit in machine architecture and is frequently used in applications, such as parity generators. The CMOS (complementary metal oxide semiconductor) circuit disclosed in this article uses a small number of field-effect transistors (FETs), four P-type and three N-type, to produce the XOR function. The CMOS XOR circuit design shown utilizes seven FET transistors to obtain a high physical chip density and a minimum delay. It operates as follows: When both inputs A and B are at an up level, transistors Q2 and Q5 are on, and output node C goes to the up level through the conduction of transistor Q5 to the up level at input node A. When both inputs A and B are at a down level, transistors Q1, Q3 and Q4 are on, and output node C goes to an up level through the conduction of transistors Q3 and Q4 to Vdd. When input A is up and B is down, transistors Q1 and Q7 are on, and output node C goes to a down level through the conduction of transistor Q7 to the down level at input node B. When input A is down and B is up, transistors Q2 and Q6 are on, and output C goes to a down level through the conduction of transistor Q6 to the down level at input node A.

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