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New Configuration of CMOS-DOMINO Logic

IP.com Disclosure Number: IPCOM000039532D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Oklobdzija, VG: AUTHOR

Abstract

This article describes a circuit configuration that has all of the advantages of a CMOS-DOMINO circuit family, yet it assures consistent precharge and is "glitch-free". The structure to be used as a CMOS-DOMINO logic block has all of the advantages of CMOS-DOMINO logic as described in [*]. The function of this logic complies with all restrictions imposed on CMOS-DOMINO (no inversion possible) and has all the benefits of this logic: CMOS power requirements and speed of dynamic n-MOS logic. However, this logic family is "glitch-free", i.e., functional block f is fully precharged during each precharge period so that during the "evaluation" phase the node F (Fig.

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New Configuration of CMOS-DOMINO Logic

This article describes a circuit configuration that has all of the advantages of a CMOS-DOMINO circuit family, yet it assures consistent precharge and is "glitch-free". The structure to be used as a CMOS-DOMINO logic block has all of the advantages of CMOS-DOMINO logic as described in [*]. The function of this logic complies with all restrictions imposed on CMOS-DOMINO (no inversion possible) and has all the benefits of this logic: CMOS power requirements and speed of dynamic n-MOS logic. However, this logic family is "glitch-free", i.e., functional block f is fully precharged during each precharge period so that during the "evaluation" phase the node F (Fig. 1) cannot swing from "1" to "0" due to the redistribution of charge (as in CMOS-DOMINO logic) or swing from "1" to "0" and back to "1" (glitch) as in the CVS logic family. All of this causes the wrong value to be propagated through the logic network to the primary output(s).

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The logic also works in two phases: "Precharge" - when all the internal nodes in the functional block f are precharged to "1" logic value; "evaluation" - when the selected blocks are discharged, due to the logic value of the inputs, and this change is propagated through the logic network in a "DOMINO" fashion. There are two separate clocks applied, Cl1 and Cl2 (see Fig. 1 and timing diagram Fig. 3). The clock Cl2 is phase shifted relative to the clock Cl1 which is easily achieved by...