Browse Prior Art Database

False Lock Sensor for Floppy Phase-Locked Loops

IP.com Disclosure Number: IPCOM000039538D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Buhler, OR: AUTHOR [+4]

Abstract

This article describes circuit arrangements which solve the problem of false phase lock in a floppy disk drive control system for accommodating various drive options with close but different bit clocking rates. The disclosed circuits detect when the phase-locked loop (PLL) directing bit transfer timing has stabilized in a condition which is incorrect (false) for the types of drives currently attached to the system and invoke suitable remedial action. It has been found that some floppy disks formatted at a 250 Kbit rate are being written on at a 300 Kbit rate, thereby destroying the format. The cause of this problem is that the PLL in the dual card, which is logically assigned to locking onto a 300 Kbit rate, can lock onto a 250 Kbit rate as well.

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False Lock Sensor for Floppy Phase-Locked Loops

This article describes circuit arrangements which solve the problem of false phase lock in a floppy disk drive control system for accommodating various drive options with close but different bit clocking rates. The disclosed circuits detect when the phase-locked loop (PLL) directing bit transfer timing has stabilized in a condition which is incorrect (false) for the types of drives currently attached to the system and invoke suitable remedial action. It has been found that some floppy disks formatted at a 250 Kbit rate are being written on at a 300 Kbit rate, thereby destroying the format. The cause of this problem is that the PLL in the dual card, which is logically assigned to locking onto a 300 Kbit rate, can lock onto a 250 Kbit rate as well. BIOS cannot distinguish between 300 and 250 Kbit rates, and because of the order used, 300 Kbit rate is assumed when actually the floppy disk is formatted at a 250 Kbit rate.

(Image Omitted)

The general concept of this disclosure is not to touch the parameters of the loop which effect its performance. Instead, develop a circuit which detects false lock. If a false lock is detected, abort the read operation. False lock for the purposes of this disclosure is when the 300 Kbit phase-locked loop locks on at 250 Kbits. Three implementations of the general concept are disclosed. Fig. 1 shows an embodiment of a false lock detector which utilizes the input control voltage to the voltage controlled oscillator (VCO) portion of the PLL to determine parametri...