Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Dual Hardware Buffer for Video Display

IP.com Disclosure Number: IPCOM000039539D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Kirk, CR: AUTHOR

Abstract

This article describes an apparatus that allows the data being displayed on a monitor to be changed in constant time independent of the amount of data being changed and in a short enough time to prevent blinking of the screen. The device uses two hardware buffers in the video adapter for controlling display on the screen. The hardware buffers are controlled so that when data is being loaded into one, information for refreshing the display is being extracted from the other buffer. In the figure, a 2k RAM is used for both buffers. The high-order address bit for the refresh address is a complement for the write address. Thus, half the RAM is the refresh buffer, while the other half is a write buffer. The buffer select line is toggled by system software (not shown) causing the buffers to swap roles.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Dual Hardware Buffer for Video Display

This article describes an apparatus that allows the data being displayed on a monitor to be changed in constant time independent of the amount of data being changed and in a short enough time to prevent blinking of the screen. The device uses two hardware buffers in the video adapter for controlling display on the screen. The hardware buffers are controlled so that when data is being loaded into one, information for refreshing the display is being extracted from the other buffer. In the figure, a 2k RAM is used for both buffers. The high-order address bit for the refresh address is a complement for the write address. Thus, half the RAM is the refresh buffer, while the other half is a write buffer. The buffer select line is toggled by system software (not shown) causing the buffers to swap roles. The control lines shown are from adapter logic and are used to control the dual hardware buffer system. The two buffers in the video adapter allow system software to store data for a new display screen in one buffer while the screen is being refreshed from the other buffer. When all the data required for the new screen has ben loaded, a single command is issued to the adapter under software control and causes the new data to be displayed. The data is changed within 1/60 second, and, as a result, no glitches are seen on the display screen.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]