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DC Testable Memory Cell for Diode-Transistor Logic Chip

IP.com Disclosure Number: IPCOM000039541D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR [+2]

Abstract

The disclosed memory cell may be used on a logic masterslice, since it operates over a range of supplies and does not require AC testing. DC testability has been accomplished by designing the memory cell to have a noise margin greater than or equal to that of an internal cell. This test method is important to the user because he does not require a new masterslice for test purposes, if he changes the array organization. The user can also operate over a range of power supplies, which allows him to widen his supply tolerances or lower his circuit power by lowering the supply. The circuit operation can be seen as a shift in control. Transistors T1 and T3 set a specific state in the write mode. In the write mode, transistors T2 and T3 maintain the state previously set by the write pulse.

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DC Testable Memory Cell for Diode-Transistor Logic Chip

The disclosed memory cell may be used on a logic masterslice, since it operates over a range of supplies and does not require AC testing. DC testability has been accomplished by designing the memory cell to have a noise margin greater than or equal to that of an internal cell. This test method is important to the user because he does not require a new masterslice for test purposes, if he changes the array organization. The user can also operate over a range of power supplies, which allows him to widen his supply tolerances or lower his circuit power by lowering the supply. The circuit operation can be seen as a shift in control. Transistors T1 and T3 set a specific state in the write mode. In the write mode, transistors T2 and T3 maintain the state previously set by the write pulse. Current will flow through the LBSD (when T3 is on) or into the base of T2 (when T2 is on) depending upon previous data. Whenever a read pulse is given, the data from node N2 is transferred to the data out line.

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