Browse Prior Art Database

Dynamic Ram Address Relocation Circuit

IP.com Disclosure Number: IPCOM000039555D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Anderson, KL: AUTHOR [+4]

Abstract

For the purpose of address translation and part number reduction in a partially good random-access memory program, an address buffer and associated address relocation memory is featured. The address buffer is composed of an input latch 10 which provides selected switchable complementary output signals. These latch output signals are coupled through a pair of transfer devices 11 and 12, controlled by non-volatile fault location address circuits 13 and 14. The outputs of devices 11 and 12 are coupled to nodes N10 and N20 which are cross-coupled to sets of devices 15 and 16 and 17 and 18 which provide true (T) and complementary (C) address signals to drive the memory address decoders (not shown).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Dynamic Ram Address Relocation Circuit

For the purpose of address translation and part number reduction in a partially good random-access memory program, an address buffer and associated address relocation memory is featured. The address buffer is composed of an input latch 10 which provides selected switchable complementary output signals. These latch output signals are coupled through a pair of transfer devices 11 and 12, controlled by non-volatile fault location address circuits 13 and 14. The outputs of devices 11 and 12 are coupled to nodes N10 and N20 which are cross-coupled to sets of devices 15 and 16 and 17 and 18 which provide true (T) and complementary (C) address signals to drive the memory address decoders (not shown). The transfer devices under control of the non-volatile fault location memory circuits 13 and 14 are deactivated if these circuits are left intact. The address buffer will then function in the normal manner. The fault location memory is any non-volatile method of storing the fault location, i.e., fuses, PROMS, etc.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]