Browse Prior Art Database

Software-Controlled Address Translation

IP.com Disclosure Number: IPCOM000039558D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Wingert, JA: AUTHOR

Abstract

Small personal computers operate in an environment where a software or microcode control program interprets an application program which is the output of a compiler (e.g. BASIC). Many of these personal computers address the program and data by means of one or several base registers. These base registers usually provide addressability in increments (e.g., 64K) which are less than the entire amount of attached storage. The control program can make these addressing restrictions transparent to the application program by implementing a virtual memory algorithm. Since the expense of hardware necessary to perform address translation would be prohibitive, to add to an existing machine, a software only solution is disclosed below.

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Software-Controlled Address Translation

Small personal computers operate in an environment where a software or microcode control program interprets an application program which is the output of a compiler (e.g. BASIC). Many of these personal computers address the program and data by means of one or several base registers. These base registers usually provide addressability in increments (e.g., 64K) which are less than the entire amount of attached storage. The control program can make these addressing restrictions transparent to the application program by implementing a virtual memory algorithm. Since the expense of hardware necessary to perform address translation would be prohibitive, to add to an existing machine, a software only solution is disclosed below. Several steps are needed to allow the system to support virtual memory without the corresponding address translate hardware. First, the addressability of the base registers IS restricted to force invalid address exceptions, and, second, a directory table is set up to provide address translation. To keep data transfer times reasonable and to efficiently use storage, the control program artificially restricts the addressability of the hardware base registers in order to divide the data and program space into manageable units ("pages"). These units can be any convenient size, for example, 4K. A reference outside one of these "pages" will cause an invalid address exception. This restriction is implemented in a computer having 64K memory segments by causing the compiler to set the logical origin of the application program being compiled at 60K. The compiler is modified to create a directory table of the logical page addr...