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Circuit Arrangement for Memory Search

IP.com Disclosure Number: IPCOM000039559D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A bipolar associative cell has been proposed for semiconductor devices which may be written to and with which one may compare data with the content of the cell. It provides simple circuitry for fast table lookups. (Image Omitted) In a previous design, table lookup is accomplished with a standard random-access memory (RAM) in combination with a large array of compare circuits. This permits the chip to be used as a regular RAM. However, the compare circuits and associated wiring require a large area which, in turn, forces the memory cells to lay in excessively wide pitches. When the chip is used as a directory or DLAT, an extra stage of compare circuit is in the delay path. When the chip is used as a regular RAM, half of the chip area is wasted.

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Circuit Arrangement for Memory Search

A bipolar associative cell has been proposed for semiconductor devices which may be written to and with which one may compare data with the content of the cell. It provides simple circuitry for fast table lookups.

(Image Omitted)

In a previous design, table lookup is accomplished with a standard random- access memory (RAM) in combination with a large array of compare circuits. This permits the chip to be used as a regular RAM. However, the compare circuits and associated wiring require a large area which, in turn, forces the memory cells to lay in excessively wide pitches. When the chip is used as a directory or DLAT, an extra stage of compare circuit is in the delay path. When the chip is used as a regular RAM, half of the chip area is wasted. The basic problem, then, is that excessively large area is wasted in each application.

(Image Omitted)

The proposal suggests a memory search array where a small search cell and a fast search access are possible (Fig. 1). This circuit, with vertical match line (ML), is essentially a regular RAM cell with pullup resistors. However, the read/write devices and the flip-flop transistors are arranged in the "compare" configuration. The cell is smaller than previous designs because T3 and T4, used to reduce SER, are also used as the read/write devices. A layout scheme for the search cell (Fig. 2) indicates the PolySi bases 1 and the trenches 2. The match line may run vertically or horizontally. Layout optimization in this configuration is relatively simple since it does not have to fit some...