Browse Prior Art Database

DYNAMIC RAMs REFRESH CIRCUITRY

IP.com Disclosure Number: IPCOM000039565D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Romero, HG: AUTHOR [+2]

Abstract

The figure illustrates the use of minimum circuitry to refresh the display list dynamic random-access memories (RAMs) using the system bus refresh signal. This eliminates the need for a dynamic RAM controller on the processor card. In using a dynamic RAM, a designer is always faced with the perplexity of how he is going to refresh the memory so that no data will be lost. The dynamic RAM remembers data by storing charge on a capacitor. Because the charge will leak away over a period of time, it is necessary to access the data in the cell (capacitor) periodically in order to fully restore the stored charge while it is still at a sufficiently high level to be properly detected. For the dynamic RAM, any Row Address Strobe (-RAS) sequence will fully refresh an entire row of 256 bits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

DYNAMIC RAMs REFRESH CIRCUITRY

The figure illustrates the use of minimum circuitry to refresh the display list dynamic random-access memories (RAMs) using the system bus refresh signal. This eliminates the need for a dynamic RAM controller on the processor card. In using a dynamic RAM, a designer is always faced with the perplexity of how he is going to refresh the memory so that no data will be lost. The dynamic RAM remembers data by storing charge on a capacitor. Because the charge will leak away over a period of time, it is necessary to access the data in the cell (capacitor) periodically in order to fully restore the stored charge while it is still at a sufficiently high level to be properly detected. For the dynamic RAM, any Row Address Strobe (-RAS) sequence will fully refresh an entire row of 256 bits. To ensure that all cells remain sufficiently refreshed, all 256 rows must be refreshed every 4 milliseconds. During a refresh cycle the system drives - REFRESH active low and drives system addresses zero through seven [+SA(0-7)]. A short time later the refresh logic drives - SMEMR active. This in turn starts a read memory cycle which occurs on the display list RAM in the display adapter. The system addresses + SA(0-7) are incremented by one each refresh cycle, so a different row address is refreshed each time, thereby refreshing every row address. One system refresh cycle occurs every 15 microseconds. This ensures that all 256 rows of the dynamic RAM are ref...