Browse Prior Art Database

Increased Contact Area Through Overetching of Vias

IP.com Disclosure Number: IPCOM000039567D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+2]

Abstract

Overetching of vias/contacts to add surface area for the purpose of lowering a semiconductor's contact resistance is reported. As VLSI semiconductor geometries are made smaller, contact areas are reduced in the scaling process. Since contact resistance is inversely proportional to contact area, a reduction in contact dimensions will result in a higher contact resistance. Fig. 1 shows the cross-section of a typical contact via. Metal (M1) is covered with an oxide insulator which is etched to endpoint to open a contact hole and expose contact area A. By adding a vertical dimension to the contact area A, some additional contact area is gained and this results in lowering the contact resistance. By overetching M1, as shown in Fig. 2, additional contact areas B and C and their opposite sides (not shown) are added to area A.

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Increased Contact Area Through Overetching of Vias

Overetching of vias/contacts to add surface area for the purpose of lowering a semiconductor's contact resistance is reported. As VLSI semiconductor geometries are made smaller, contact areas are reduced in the scaling process. Since contact resistance is inversely proportional to contact area, a reduction in contact dimensions will result in a higher contact resistance. Fig. 1 shows the cross-section of a typical contact via. Metal (M1) is covered with an oxide insulator which is etched to endpoint to open a contact hole and expose contact area A. By adding a vertical dimension to the contact area A, some additional contact area is gained and this results in lowering the contact resistance. By overetching M1, as shown in Fig. 2, additional contact areas B and C and their opposite sides (not shown) are added to area A. Contact metalization takes advantage of the added areas, resulting in a lower contact resistance and minimizes the scaling factors used to achieve a higher chip density.

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