Browse Prior Art Database

Current Sense Static Bipolar Random-Access Memory Cell

IP.com Disclosure Number: IPCOM000039573D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Blum, DW: AUTHOR

Abstract

In this current sense cell, sensing and writing is done through two NPN transistors added to a basic complementary transistor switch (CTS) latch. These two NPN transistors, serving as the bit line interface, are formed in existing P-type regions by the addition of an N+ emitter diffusion. The resulting random-access memory (RAM) cell has improved access time, requires smaller power supply voltage differential (Vhigh - Vlow), and has improved alpha particle immunity. The CSC cell is shown in the figure. The cell utilizes transistors 3, 4, 5, and 6 to form the basic (CTS) latch. NPN transistors 1 and 2 have been added to serve as the bit line interface. A word line WL is selected by pulling it up by approximately 300 mV while simultaneously increasing the current. The same procedure is used for both read and write operations.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Current Sense Static Bipolar Random-Access Memory Cell

In this current sense cell, sensing and writing is done through two NPN transistors added to a basic complementary transistor switch (CTS) latch. These two NPN transistors, serving as the bit line interface, are formed in existing P- type regions by the addition of an N+ emitter diffusion. The resulting random- access memory (RAM) cell has improved access time, requires smaller power supply voltage differential (Vhigh - Vlow), and has improved alpha particle immunity. The CSC cell is shown in the figure. The cell utilizes transistors 3, 4, 5, and 6 to form the basic (CTS) latch. NPN transistors 1 and 2 have been added to serve as the bit line interface. A word line WL is selected by pulling it up by approximately 300 mV while simultaneously increasing the current. The same procedure is used for both read and write operations. Reading the cell is accomplished by increasing the current through the bit line BL and sensing the increased current through either T1 or T2 depending on the cell state. The inverse NPN transistor T1 or T2 on the low voltage side of the cell will turn on harder, and the differential current on the bit lines BL0 and BL1 is detected in sense amplifier SA. Bit line selection for a read operation is done at the sense amplifier or at the bit line current source. Access delay is reduced because the current differential begins to increase as soon as word line pull-up begins. Charge going to collector-substrate capacitance CCS enhances the read current. The cell is written by pulling current through the emitter of trans...