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Enhancement of Memory Card Redundant Bit Usage Via Simplified Fault Alignment Exclusion Implementation

IP.com Disclosure Number: IPCOM000039575D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Arlington, DL: AUTHOR [+2]

Abstract

A method is described for enhancing redundancy at the card level by providing a plurality of registers such that one redundant bit can replace bits in any of "n" chips. The advantage of this method over previous card level redundancy techniques is that more than one chip failure per chip level can be accommodated. Memory cards are often expanded by adding banks of memory modules or chips having input/output (I/O) lines dotted to I/O of previous banks or levels. This is illustrated in Fig. 1 wherein the top row represents the base card, e.g., a 4-byte-wide bank, 256 bit chips, one chip deep, thus providing a one-megabyte card. A 2x expansion is obtained by adding another bank of chips with input/output (I/O) dotted to the first bank. By adding two more banks, 4 megabytes with each bit 4 chips deep is obtained.

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Enhancement of Memory Card Redundant Bit Usage Via Simplified Fault Alignment Exclusion Implementation

A method is described for enhancing redundancy at the card level by providing a plurality of registers such that one redundant bit can replace bits in any of "n" chips. The advantage of this method over previous card level redundancy techniques is that more than one chip failure per chip level can be accommodated. Memory cards are often expanded by adding banks of memory modules or chips having input/output (I/O) lines dotted to I/O of previous banks or levels. This is illustrated in Fig. 1 wherein the top row represents the base card, e.g., a 4-byte-wide bank, 256 bit chips, one chip deep, thus providing a one- megabyte card. A 2x expansion is obtained by adding another bank of chips with input/output (I/O) dotted to the first bank. By adding two more banks, 4 megabytes with each bit 4 chips deep is obtained.

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Redundancy is normally achieved in a redundant bit swap based on a single pointer address in a register. The 4 chips of the redundant bit R would have to swap for bad bit #1. However, if bit #1 is only bad due to a single bad chip X, then 3/4 of the selectable memory of bit #1 is good. Thus, 3 good chips of the #1 bit are replaced unnecessarily. By setting the number of pointer address registers equal to the number of chip levels, e.g., four in the 4-megabyte card of Fig. 1, this cause of inefficient redundancy is avoided. As diagrammed in Fig. 2, the pointer registers P.R. can be loaded with different addresses for each chip level of the bits. In Fig. 2, the address of bad bit A is bit #1 of chip level 4 and is stored in the number 4 level of the pointer register P.R. The address selected for use is determined by the level of chips that is selected during that cycle. Therefore, chip select signals that activate the arrays are also used to select the register to be fed into redundant bit swap logic RBSL via a multiplexer M. As shown in Fig. 2, this allows the 4 bits that make up the one redundant bit to be swapped individually for 4 bad chips in 4 different bit...