Browse Prior Art Database

New Context Bit

IP.com Disclosure Number: IPCOM000039576D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

The present invention proposes a new context bit to initiate sequential prefetching of instruction lines. This helps minimize misses for sequential instruction lines when a new context is encountered in the execution of instructions. When a processor begins to execute a sequence of instructions that have not been executed in a long time, many of the instruction lines that are about to be used will not be in the cache. Most instruction reference patterns display strong sequentiality, i.e., if a line is referenced, it is very likely that the next sequential line will also be referenced by the processor for the purpose of fetching instructions. A cache may be considered to contain a collection of recently executed contexts with their most recently executed lines.

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New Context Bit

The present invention proposes a new context bit to initiate sequential prefetching of instruction lines. This helps minimize misses for sequential instruction lines when a new context is encountered in the execution of instructions. When a processor begins to execute a sequence of instructions that have not been executed in a long time, many of the instruction lines that are about to be used will not be in the cache. Most instruction reference patterns display strong sequentiality, i.e., if a line is referenced, it is very likely that the next sequential line will also be referenced by the processor for the purpose of fetching instructions. A cache may be considered to contain a collection of recently executed contexts with their most recently executed lines. If execution continues to remain in contexts that are mostly cache resident, misses will tend to occur as a result of branches that are taken differently on the most recent execution than on previous executions. That is, this type of "steady state" is likely not to involve misses to several sequential instruction lines. This invention provides a bit, called the new context bit (NCB), which indicates that sequential prefetching is to be performed. When the NCB is set, on each instruction fetch MRU change, if the next sequential line is not in the cache, it is prefetched. When the NCB is clear, instruction fetching proceeds as it otherwise would for the particular machine, including any other...