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DRAM Write/Erase Function

IP.com Disclosure Number: IPCOM000039577D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Kilmer, CA: AUTHOR [+2]

Abstract

This function allows block write/erase (BW/E) of dynamic random-access memory (DRAM) in a very short cycle time by using an on-chip refresh address counter (RAC) and a transfer mode operation. The function transfers the previous data, available at the sense amplifiers, to a RAC allowing the user to perform a BW/E at very fast cycle times without the overhead of keeping track of addresses. State-of-the-art CMOS DRAM [*] operates with the bit lines at a 1/2 Vdd potential to reduce power required. Bit lines are held in an active Vdd or ground state from the set time of one cycle until the beginning of the following cycle, i.e., during standby. At the beginning of the cycle, the bit lines are equalized to form the Vdd/2 reference level from which a positive or negative signal is applied from the cell.

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DRAM Write/Erase Function

This function allows block write/erase (BW/E) of dynamic random-access memory (DRAM) in a very short cycle time by using an on-chip refresh address counter (RAC) and a transfer mode operation. The function transfers the previous data, available at the sense amplifiers, to a RAC allowing the user to perform a BW/E at very fast cycle times without the overhead of keeping track of addresses. State-of-the-art CMOS DRAM [*] operates with the bit lines at a 1/2 Vdd potential to reduce power required. Bit lines are held in an active Vdd or ground state from the set time of one cycle until the beginning of the following cycle, i.e., during standby. At the beginning of the cycle, the bit lines are equalized to form the Vdd/2 reference level from which a positive or negative signal is applied from the cell. A state-of-the-art feature, sometimes referred to as transfer mode operation, transfers the previous data available at the sense amplifiers to any other word line in a fast cycle. This fast transfer (FT) is accomplished by inhibiting the equalization of the bit lines at the beginning of the cycle. When a wordline is selected, the bit line data is transferred directly into the newly selected cells, thereby storing new data on that entire word line.

The cycle time is reduced since no equalization time and no column timing is required. By coupling the FT described above to an RAC, the user can perform a BW/E at very fast cycle times. In this mode,...