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Random Pattern Testability of the Logic Surrounding Memory Arrays

IP.com Disclosure Number: IPCOM000039582D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 5 page(s) / 47K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+5]

Abstract

The cutting algorithm 1 may be used in computing a lower bound of the detection probability of faults surrounding memory arrays. If the array and the logic surrounding it are such that there is a complete isolation between the control address logic, the prelogic and the postlogic (see Fig. 1), then the probability that a sequence of length M will detect a fault in either the prelogic or the postlogic is given by where L is the number of fresh reads, and pr is the restricted exposure probability. The restricted exposure probability can be computed by removing the array, and connecting the prelogic and postlogic together (see Fig. 1). This transform leads to a combinational logic for which several existing algorithms may be used.

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Random Pattern Testability of the Logic Surrounding Memory Arrays

The cutting algorithm 1 may be used in computing a lower bound of the detection probability of faults surrounding memory arrays. If the array and the logic surrounding it are such that there is a complete isolation between the control address logic, the prelogic and the postlogic (see Fig. 1), then the probability that a sequence of length M will detect a fault in either the prelogic or the postlogic is given by where L is the number of fresh reads, and pr is the restricted exposure probability. The restricted exposure probability can be computed by removing the array, and connecting the prelogic and postlogic together (see Fig. 1). This transform leads to a combinational logic for which several existing algorithms may be used.

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A fresh read is defined as the first read from a memory address after a write to that address. Simulation techniques can be used to compute both pr and L. The cutting algorithm is an analytical tool which currently handles faults in a strictly combinatorial environment. Since no simulation capability is available through the cutting algorithm, different methods are required in order to handle the faults surrounding the array. Moreover, the assumption of having complete isolation between the prelogic and the postlogic is too restrictive, does not hold in real designs, and therefore has to be removed.

(Image Omitted)

This article will show:

1) how to compute analytically the expected number of

fresh reads;

2) how to migrate the sequence detection probabilities

to pattern detection probabilities;

3) how to handle feedaround logic between the prelogic

and the postlogic using the cutting algorithm, and

4) how to handle multiport arrays. Computation of the Expected Number of Fresh Reads The expected number of fresh reads from a memory array depends on the type of array and its behavior. The number of fresh reads from a memory array is a random variable. The examples used here are for a single port array with one read/write control and a single port array with separate read/write controls.

(Image Omitted)

In both cases, it is assumed that the read/write control lines are independent of the address select lines. Case 1: A Single Port Array with One Read/Write Control In this case the probability of read and probability of write add up to one. The Markov chain of Fig. 2 describes the process of achieving

1

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fresh reads. The state S0 is the initial state. The state S1 is the state where a specific address, say, address i, has been written into. The state S2 is the state where a fresh read has occurred from address i. The probability of writing to any address is denoted by w, and si (shown as s in Fig. 2) denotes the probability that address i is being selected. We assume that the read/write line is independent of the address lines. The solution of this Markov chain lead to Pn(S2)=w(1-w)si[1-(1-si)n-1] (n 1) Po(S2)=0 This form...