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Browse Prior Art Database

Power Distribution for Wafer Substrates

IP.com Disclosure Number: IPCOM000039615D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Gruber, HW: AUTHOR [+3]

Abstract

A power distribution for chips packaged on a wafer substrate is disclosed. Figs. 1A and 1B show chips 1 connected by vias 3 to a power-carrying metallization 4 on the back side of wafer 2. Metallization 4, covering vias 3, forms a checkerboard pattern 5 (Fig. 2) for two voltage levels V1 and V2. The isolated individual checkerboard positions are connected in parallel by meander-type metal rails 6 (Fig. 3), bridging the different voltage levels from one metal square 5 to the next by low inductance. Chip sites 7 are positioned such that four metal squares 5 are always located directly below one chip 1. Meander-type metal rails 6, extending beyond wafer 2, are provided with knife-edge contacts (not shown) to slip into a bus powering the wafers. Chips 1 are conntected to wafer power distribution vias 3 by wire bonding (Fig.

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Power Distribution for Wafer Substrates

A power distribution for chips packaged on a wafer substrate is disclosed. Figs. 1A and 1B show chips 1 connected by vias 3 to a power-carrying metallization 4 on the back side of wafer 2. Metallization 4, covering vias 3, forms a checkerboard pattern 5 (Fig. 2) for two voltage levels V1 and V2. The isolated individual checkerboard positions are connected in parallel by meander-type metal rails 6 (Fig. 3), bridging the different voltage levels from one metal square 5 to the next by low inductance. Chip sites 7 are positioned such that four metal squares 5 are always located directly below one chip 1. Meander-type metal rails 6, extending beyond wafer 2, are provided with knife-edge contacts (not shown) to slip into a bus powering the wafers. Chips 1 are conntected to wafer power distribution vias 3 by wire bonding (Fig. 1B) or C4 joints (Fig. 1A). Metal rails 6 have holes with eyelets (not shown) which are used to wire-bond the rails to wafer metallization 4 and provide flexibility to accommodate thermal expansion. The rail system allows decoupling capacitors 8 to be placed directly between rails
6.

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