Browse Prior Art Database

Process for Borderless Polysilicon Contacts

IP.com Disclosure Number: IPCOM000039619D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Barber, JR: AUTHOR [+2]

Abstract

An increase in the circuit density of a very large-scale integrated (VLSI) circuit can be realized by incorporating a polysilicon contact with reduced borders. The process disclosed allows a significant increase in circuit density. Referring to Fig. 1, a semiconductor substrate 10 has diffusion regions 12 implanted therein. Polysilicon gate 14 and contact 16 have oxide spacers formed along their respective sides. Field oxide region 20 underlies the polysilicon contact 16. A second oxide spacer is next formed by the blanket deposition of oxide and subsequent blanket reactive ion etch. The resulting structure can be seen in Fig. 2. (Image Omitted) Next, a thin layer of oxide 24 is applied followed by a deposition of an insulating layer 26. The insulating layer 26 may be reflowed, as desired.

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Process for Borderless Polysilicon Contacts

An increase in the circuit density of a very large-scale integrated (VLSI) circuit can be realized by incorporating a polysilicon contact with reduced borders. The process disclosed allows a significant increase in circuit density. Referring to Fig. 1, a semiconductor substrate 10 has diffusion regions 12 implanted therein. Polysilicon gate 14 and contact 16 have oxide spacers formed along their respective sides. Field oxide region 20 underlies the polysilicon contact 16. A second oxide spacer is next formed by the blanket deposition of oxide and subsequent blanket reactive ion etch. The resulting structure can be seen in Fig.
2.

(Image Omitted)

Next, a thin layer of oxide 24 is applied followed by a deposition of an insulating layer 26. The insulating layer 26 may be reflowed, as desired. The resulting structure can be seen in Fig. 3. Referring to Fig. 4, contact window 28 is etched through the insulating layer 26 and oxide layer 24. The field oxide region 20 is protected from the etch process by the second oxide spacer 22. The process described reduces the border around polysilicon contacts allowing for increased circuit density.

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