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HIGH-SPEED REAL-TIME EVENT PROCESSOR

IP.com Disclosure Number: IPCOM000039627D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 16K

Publishing Venue

IBM

Related People

Elliott, JE: AUTHOR [+2]

Abstract

This article relates to an external register (XR) bus sequencer that is designed for the control of multiple real-time sequences such as for peripheral data storage devices through the external registers attached to a common bus. It is preferred that it provides an XR bus protocol used in the data storage device so that existing functional units of the data storage device can be utilized in the implementation of the sequencer. The XR Bus Sequencer overcomes a problem that is characteristic of processors that normally supply the bus sequences. The problem is that these processors have some minimum time in which they can respond to real-time events and usually some variation (jitter) in the response time.

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HIGH-SPEED REAL-TIME EVENT PROCESSOR

This article relates to an external register (XR) bus sequencer that is designed for the control of multiple real-time sequences such as for peripheral data storage devices through the external registers attached to a common bus. It is preferred that it provides an XR bus protocol used in the data storage device so that existing functional units of the data storage device can be utilized in the implementation of the sequencer. The XR Bus Sequencer overcomes a problem that is characteristic of processors that normally supply the bus sequences. The problem is that these processors have some minimum time in which they can respond to real-time events and usually some variation (jitter) in the response time. This limits the functions that can be implemented by microcode to those that can tolerate the delay and jitter in the response to an event. Processors that use interrupts to respond to real-time events have a response time that is a function of the time it takes to service an interrupt and the maximum amount of time that the interrupt can be masked or delayed while servicing higher priority interrupts. Unique hardware is required to translate the event occurrences into interrupt requests. Processors that test periodically for an event by means of a program loop have response times that are a function of the number of cycles in the loop. When more than one event must be tested at a time, the loop gets larger. If there is a possibility that the event might not occur, the program would "hang", making it necessary to have a timeout mechanism to pull the program out of the loop. This can be a counter programmed within the loop or a hardware- implemented interval timer that must be tested for timeout. To test for an event usually takes at least two instructions, one to test for the event, and the other to make the conditional branch or jump. All of these factors affect the time between consecutive samples for the event. The XR Bus Sequencer solves these problems by providing bit and byte testing instructions that sample for an event with a resolution of one instruction cycle and bit and byte setting instructions that make it possible to respond on the next instruction cycle. A cycle counter that provides "timeout" protection for cases where the programmed for event does not occur is included in the implementation of these instructions. A program utilizing these instructions can control an I/O sequence where the events usually occur in a predictable order. Multiple I/O sequences that are not synchronous to each other are often encountered in controlling an I/O process. To handle these situations, the sequencer design provides for multiple sequences, running with TDM (time division multiplex) use of the XR bus and common sequencer facilities. The current sequencer design is implemented with two sequences. This number optimizes the response time for the implementation of the sequence and controlled data...