Browse Prior Art Database

IMPROVED DECODE CIRCUITS for CMOS MEMORY ARRAYS

IP.com Disclosure Number: IPCOM000039638D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR [+3]

Abstract

A novel memory address decode circuit with precharge support circuits integrated into a decoder design for CMOS memory arrays is described. Charge distribution is a problem in NAND decoders utilized in some CMOS memory products. The self-clocking precharge scheme disclosed eliminates precharge distribution and guarantees that selected address lines are switched only when the decoder outputs are valid. (Image Omitted) The address decoder circuit in Fig. 1 normally drives only one of four select lines when clock is high. It is also utilized for precharge distribution by selecting all four select lines when clock is low.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

IMPROVED DECODE CIRCUITS for CMOS MEMORY ARRAYS

A novel memory address decode circuit with precharge support circuits integrated into a decoder design for CMOS memory arrays is described. Charge distribution is a problem in NAND decoders utilized in some CMOS memory products. The self-clocking precharge scheme disclosed eliminates precharge distribution and guarantees that selected address lines are switched only when the decoder outputs are valid.

(Image Omitted)

The address decoder circuit in Fig. 1 normally drives only one of four select lines when clock is high. It is also utilized for precharge distribution by selecting all four select lines when clock is low. By forcing high all address input lines that normally control word line (WL) selection, except the lowest order line, precharge distribution is improved and guarantees that outputs of the decoder will switch only when valid. The address lines are used in pairs to generate groups of four select lines. One pair of high address inputs, e.g., A5 and A6, and a low clock pulse decodes/selects a set of four select lines, i.e., not A5.A6, A5.not A6, not A5.A6 and A5.A6. These select lines gate T4, T5, T6 and T7. A predecoder (not shown) of A1-A2 and A3-A4 gates T2 and T3. When the clock goes low, gates T2, T3, T4, T5, T6 and T7 are selected, allowing P devices T8, T9, T10 and T11 to precharge the decoder down to node A, and deselecting WL1 through WL4. A special driver circuit shown in Fig. 2 gates T1 and guar...