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Variations of the Two-Bit Slice Incrementer Logic

IP.com Disclosure Number: IPCOM000039641D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Levy, JR: AUTHOR [+3]

Abstract

Variations of a two-bit slice incrementer are described which permit a reduction in chip layout area and power consumption because of minimum device counts. Incrementer logic is commonly utilized in combination with a register as a binary counter for instruction counting, shifting, timing and updating address and word counts in processors and channels. Combinational logic circuits which can increment a binary number by one are useful in custom logic where density, performance and power consumption are key goals. The use of a two-bit slice allows the circuit designer tradeoffs in optimizing the design in terms of speed, power and silicon utilization. There are several variations of a two-bit slice incrementer which will result in a chip area layout reduction.

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Variations of the Two-Bit Slice Incrementer Logic

Variations of a two-bit slice incrementer are described which permit a reduction in chip layout area and power consumption because of minimum device counts. Incrementer logic is commonly utilized in combination with a register as a binary counter for instruction counting, shifting, timing and updating address and word counts in processors and channels. Combinational logic circuits which can increment a binary number by one are useful in custom logic where density, performance and power consumption are key goals. The use of a two-bit slice allows the circuit designer tradeoffs in optimizing the design in terms of speed, power and silicon utilization. There are several variations of a two-bit slice incrementer which will result in a chip area layout reduction. One variation is dependent on the availability of additional external signals, and the other is dependent upon tighter controls of device electrical characteristics. Fig. 1 shows an incrementer independent of technology and consisting of 15 transistors when implemented in NMOS. The lower order bit position is odd (AODD) and the higher order bit position is even (AEVEN). A 2 N bit incrementer can be formed by connecting N 2-bit slices in series. The odd bit circuit consists of a 3-device NAND and a 4-device OAI circuit. The even bit circuit consists of a 2-device inverter, a 3-device NOR and a 3-device XNOR circuit. The logical output sum of the low and high order bit positions are labeled not sum odd (SO) and not sum even (SE), respectively. The odd bit position logical carry-in (CIN) is a carry-even (CE) signal and the carry-out line is a logical not carry-out (CO) signal. The output of the even bit circuit is a logical CE. The total circuit delay is primarily dependent on the carry delay which ripples through the NAND and NOR of each slice; therefore, these circuits (NAND and NOR) are...