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CONTROL of NEGATIVE/POSITIVE MODE in IMAGE and BORDER AREAS

IP.com Disclosure Number: IPCOM000039642D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Kobayashi, M: AUTHOR [+3]

Abstract

This article describes a circuit for controlling the negative/positive mode displayed in the image area and border area of a display surface. The circuit is applied with a control signal for selecting negative or positive mode in the both areas. Fig. 1 shows a display surface of a display unit which includes a display area 1 and a border area 2. The display unit has the following two display modes: (Image Omitted) Displayed Image Background Border Area Display Mode 1 Black White White Display Mode 2 White Black Black Referring to Fig. 2 showing a circuit for controlling the display operations, a video signal of high or low level, as shown in Fig. 3A is applied to an input of an Exclusive OR gate 3.

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CONTROL of NEGATIVE/POSITIVE MODE in IMAGE and BORDER AREAS

This article describes a circuit for controlling the negative/positive mode displayed in the image area and border area of a display surface. The circuit is applied with a control signal for selecting negative or positive mode in the both areas. Fig. 1 shows a display surface of a display unit which includes a display area 1 and a border area 2. The display unit has the following two display modes:

(Image Omitted)

Displayed Image Background Border Area Display Mode 1 Black White White Display Mode 2 White Black Black Referring to Fig. 2 showing a circuit for controlling the display operations, a video signal of high or low level, as shown in Fig. 3A is applied to an input of an Exclusive OR gate 3. A control signal (CONTROL) of high or low level for selecting the display mode is applied to the other input of the Exclusive OR gate 3. Vertical blank signal (V-BLANK) and horizontal blank signal (H-BLANK) are applied to inputs of a blank signal generator 4 which generates horizontal-vertical blank signal (VHVB), as shown in Fig. 3B. Display Mode 1 The high level control signal is applied to the input of the Exclusive OR gate 3. In this mode, the Exclusive OR gate 3 operates as an inventor circuit.

During a border area scanning period, the Exclusive OR gate 3 generates the signal V1 of high level, as shown in Fig. 3C. During this scanning period, both inputs of NAND gate 5 are high level, whereby the NAND gat...