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Bidirectional Open Drain Latching Buffer Circuit

IP.com Disclosure Number: IPCOM000039646D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Kiley, DB: AUTHOR

Abstract

An open drain latching buffer circuit with built-in pull-up devices is used to both drive and receive from open drain nets utilizing a common I/O port. A known keyboard/controller interface for IBM personal computers (PCs) in a net consists of a keyboard clock line, a keyboard data line, a transmit data line, a keyboard inhibit line and a keyboard disconnect line. Off chip open drain buffers, a manual keyboard disconnect switch and five pull-up resistors complete the interface. Fig. 1 is a block diagram of a keyboard/controller interface which utilizes a bidirectional keyboard clock line (keyboard clock and keyboard inhibit), a keyboard data line (send/receive) and a keyboard disconnect line.

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Bidirectional Open Drain Latching Buffer Circuit

An open drain latching buffer circuit with built-in pull-up devices is used to both drive and receive from open drain nets utilizing a common I/O port. A known keyboard/controller interface for IBM personal computers (PCs) in a net consists of a keyboard clock line, a keyboard data line, a transmit data line, a keyboard inhibit line and a keyboard disconnect line. Off chip open drain buffers, a manual keyboard disconnect switch and five pull-up resistors complete the interface. Fig. 1 is a block diagram of a keyboard/controller interface which utilizes a bidirectional keyboard clock line (keyboard clock and keyboard inhibit), a keyboard data line (send/receive) and a keyboard disconnect line. An open drain data latching buffer, an open drain clock latching buffer, a manual keyboard disconnect switch and a precharge drive line for the latching buffers complete the interface configuration. The keyboard clock line and data bus line are bidirectional, reducing by two the number of I/O pins previously required. A precharge cycle is utilized to replace the external pull-up resistors in a known design. Fig. 2 shows a cross-coupled bidirectional latching data buffer circuit with a plurality of drivers and receivers attached to nodes A and B of the buffer along a single wire send/receive bus. Each open drain driver is a two-input NAND circuit driven by an enable line and data input line. A second cross-coupled bidirectional latching buffer circuit (not shown) is utilized for clock control signals between the attached I/O devices and a controller. Both latching buffer circuits function in the same manner and are precharged each cycle. After the initial timing synchronization (handshaking procedure) between the controller and a keyboard, data transmission begins and any or all attached I/O on either node A or node B may receive from the se...