Browse Prior Art Database

Microcoded Self Exerciser

IP.com Disclosure Number: IPCOM000039648D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Fidishun, PD: AUTHOR

Abstract

This article presents a method of testing a Writable Control Storage (WCS) array. The technique uses combinations of valid microcode words to exercise the entire WCS in an operational environment. The test is conducted at full machine speed exercising a WCS address each machine cycle. It uses the built-in error detection schemes of WCS parity and sequence checking to detect and report faults. Failure isolation is enhanced down to the chip level with the aid of the Processor Controller (PC) and Trace arrays. In the design, the time required to conduct the test is minimized, and the PC code required to support the exerciser is also minimized. The WCS is tested by using operationally valid micro-words for patterns and existing Parity and Sequence checks to report errors.

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Microcoded Self Exerciser

This article presents a method of testing a Writable Control Storage (WCS) array. The technique uses combinations of valid microcode words to exercise the entire WCS in an operational environment. The test is conducted at full machine speed exercising a WCS address each machine cycle. It uses the built- in error detection schemes of WCS parity and sequence checking to detect and report faults. Failure isolation is enhanced down to the chip level with the aid of the Processor Controller (PC) and Trace arrays. In the design, the time required to conduct the test is minimized, and the PC code required to support the exerciser is also minimized. The WCS is tested by using operationally valid micro-words for patterns and existing Parity and Sequence checks to report errors. The test runs sequentially through the WCS like a large microinstruction and recycles on the last address with a PC soft interrupt. The amount of PC code and hardware required to create an exerciser was minimized by taking maximum advantage of existing facilities. This was possible because the exerciser is executed like normal microcode. The facilities used are WCS parity, trace arrays and the scanning system. Existing WCS parity reporting methods may be used to report parity errors during the execution of the exerciser microcode. Trace arrays may be used to identify the failing address by being accessed after a WCS parity error reports a failure. Trace array information will yield the failing address of the WCS. An existing scan system may be used to scan out the existing Control Store Data Register (CSDR) to identify the failing bit or bits. The scanned CSDR data will be compared to the stored image of the data set at the WCS address location specified by the trace array information. The isolation using this method is to the bit level in the failing chip. The basic concept is to develop a small number of valid micro- words which can be executed like...