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High Performance Transfer Gate Circuit to Implement Incrementer/ Decrementer Function

IP.com Disclosure Number: IPCOM000039662D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Correale, A: AUTHOR

Abstract

Transfer gates and simple primitive logic can be configured to provide a circuit which will increment/decrement a count by one. The disclosed circuits provide this function using only one pair of transfer gates, an inverter and an exclusive-OR per bit. These realizations result in reduced area and improved overall performance. Fig. 1 illustrates the truth table for the decrement-by-1 function. The Boolean equation for the Carry-out (borrow) is Cout = Cin OR A. The Boolean equation for the decremented bit output is Zn = A XNOR Cin. (Image Omitted) Fig. 2A illustrates a single-bit circuit to implement the Carry- out (borrow) function using two transfer gates and an inverter. Fig.

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High Performance Transfer Gate Circuit to Implement Incrementer/ Decrementer Function

Transfer gates and simple primitive logic can be configured to provide a circuit which will increment/decrement a count by one. The disclosed circuits provide this function using only one pair of transfer gates, an inverter and an exclusive- OR per bit. These realizations result in reduced area and improved overall performance. Fig. 1 illustrates the truth table for the decrement-by-1 function. The Boolean equation for the Carry-out (borrow) is Cout = Cin OR A. The Boolean equation for the decremented bit output is Zn = A XNOR Cin.

(Image Omitted)

Fig. 2A illustrates a single-bit circuit to implement the Carry- out (borrow) function using two transfer gates and an inverter. Fig. 2B illustrates a single-bit circuit realization to implement the overall decrement function using two transfer gates, an inverter and an exclusive OR. The data input, An, is applied to the input of the inverter and the gate of transfer device Q1. The output of the inverter is applied to the gate of transfer device Q2 and to one of the two inputs of the XOR. The source of transfer device Q2 and the second input of the XOR is connected to the carry-in signal, Cin. The source of transfer device Q1 is connected to VDD. The drains of both transfer devices are commoned and provide the carry- out Cout of the bit. This n-th bit carry-out provides the carry-in to the n-1 bit. The output of the XOR, Zn, is the decremented bit output. The circuit of Fig. 2B operates as follows: The application of a "1" to the Cin input results in the Cout being a "1" independent of the An input. This occurs as both transfer device sources are at a "1" and the selection of either device results in a "1" being propagated to the Cout node. The decremented output is the same logical value as the An input. Hence, when the Cin signal is a "1", the output of the decrementer is the same as the input. The application of a "0" to the Cin

(Image Omitted)

input causes the following: The "0" propagates to one input of the XOR and to the source of transfer device Q2. For the case when An is a "0", the output of the inverter is a "1" which causes transfer device Q2 to conduct, thereby propagating the Cin signal to the Cout node. The output of the inverter being a "1" also causes the XOR to switch to a "1". For the case where An is a "1", the transfer device Q2 is turned off and device Q1 conducts, thereby propagating a "1" to the Cout node independent of the Cin polarity. The output of the XOR now switches to a "0". This performs the decrement operation. The same circuit can be configured to perform the increment operation. Fig. 3 illustrates the truth table for the increment-by-1 function. The Boolean equation for the Carry-out is Cout = Cin AND A. The Boolean equation for the incremented bit output is Zn = A XOR Cin. For the increment operation, the following modifications are necessary: The Cin signal is now ap...