Browse Prior Art Database

Fuse Circuit With Zero DC Current

IP.com Disclosure Number: IPCOM000039673D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Fischer, W: AUTHOR [+4]

Abstract

A fuse circuit for embedded arrays with word line redundancy is described which provides DC voltage levels V0 = 0V, VH but draws no DC current. This feature is essential as it ensures that leakage current measurements, which are a simple first test for CMOS logic chips, are not falsified by the fuse circuit. The figure shows the circuit which consists of a set driver, a coupling capacitor CC, a fuse, and a latch. The set driver generates a rising voltage VS which is derived from the rising power supply signal VH during power-on. Voltage VS is coupled by capacitor CC to the latch, setting it to the "0" state (output voltage V0 = 0V) if the resistance of the fuse is high (fuse blown or cut). If the resistance of the fuse is low (fuse not blown), the latch goes to the "1" state (V0 = VH).

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Fuse Circuit With Zero DC Current

A fuse circuit for embedded arrays with word line redundancy is described which provides DC voltage levels V0 = 0V, VH but draws no DC current. This feature is essential as it ensures that leakage current measurements, which are a simple first test for CMOS logic chips, are not falsified by the fuse circuit. The figure shows the circuit which consists of a set driver, a coupling capacitor CC, a fuse, and a latch. The set driver generates a rising voltage VS which is derived from the rising power supply signal VH during power-on. Voltage VS is coupled by capacitor CC to the latch, setting it to the "0" state (output voltage V0 = 0V) if the resistance of the fuse is high (fuse blown or cut). If the resistance of the fuse is low (fuse not blown), the latch goes to the "1" state (V0 = VH). To support the "0" state, an unsymmetrical latch is preferred (see W/L ratios). The set driver, which may be implemented as a Schmitt trigger or a similar circuit, is used as a dv/dt amplifier for the input signal VI = VH . Its switching level for VID should be high. A delay stage, consisting of resistor RD and capacitor CD, delays and integrates VI to suppress noise on VH.

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