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CMOS Driver Circuit

IP.com Disclosure Number: IPCOM000039676D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Mitby, JS: AUTHOR [+3]

Abstract

This circuit is an interface to CMOS chips that may provide a down level of voltage from 0 to .5 volts and an up level ranging from 1.55 to 2.2 volts, the latter being a rather unusual voltage range, while providing good response time and stability while driving transmission lines with various kinds of loading conditions. The circuit enables slew rate limiting and feedback in an off chip driver and may be incorporated in a CMOS I/O BUS tri-state driver. The circuit is composed of N-channel standard threshold devices (Q2, Q6, Q7, Q8, Q10, Q11, Q13, Q27, Q28), N-channel low threshold devices (Q17- Q26), and P-channel standard threshold devices (Q1, Q3-Q5, Q9, Q12, Q14-Q16). The circuit has the signal input A0; tri-state enables B0 and DI (data inhibit), and output P10.

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CMOS Driver Circuit

This circuit is an interface to CMOS chips that may provide a down level of voltage from 0 to .5 volts and an up level ranging from 1.55 to 2.2 volts, the latter being a rather unusual voltage range, while providing good response time and stability while driving transmission lines with various kinds of loading conditions. The circuit enables slew rate limiting and feedback in an off chip driver and may be incorporated in a CMOS I/O BUS tri-state driver. The circuit is composed of N-channel standard threshold devices (Q2, Q6, Q7, Q8, Q10, Q11, Q13, Q27, Q28), N-channel low threshold devices (Q17- Q26), and P-channel standard threshold devices (Q1, Q3-Q5, Q9, Q12, Q14-Q16). The circuit has the signal input A0; tri-state enables B0 and DI (data inhibit), and output P10. The input signal A0 is inverted four times through transistors Q1-Q11 and twice through transistors Q12-Q21. The Nand gates composed of Q3-Q8 and Q12-Q15 replace inverters in order to incorporate the tri-state feature of the driver. With a logically low voltage applied at A0, the driver behaves in a standard manner driving the output to a valid low voltage level; however, with a logically high voltage applied at A0, the unique features of the circuit are demonstrated. With the driver enabled and A0 switching to a high level transistor Q13, Q7 and Q8 behave as a resistor between node A and ground. Node A is forced low, turning on Q16. Current supplied through Q16 to the standard clamp formed by Q18 and Q19 causes the voltage at node 1 to rise approximately one N-channel threshold voltage above the desired output voltage. As the voltage at node 1 increases, the output voltage follows, but is level shifted down by the threshold voltage of Q21. The active capacitor Q20 slew rate limits the voltage at node 1 which results in a slew rate limit on the output since Q21 is a common drain configuration. The sle...