Browse Prior Art Database

Multi-Technology Chip Carrier

IP.com Disclosure Number: IPCOM000039677D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Butz, M: AUTHOR [+4]

Abstract

The chip carrier comprises a multilayer ceramic base carrier 1 on which a multilayer flexible polyimide carrier 2 is deposited. Chips 3 are connected to flexible carrier 2 by C4 connections 5. Ceramic carrier 1 comprises power distribution layers 6 (sandwich power plane structure). Conductive layers 7 of carrier 2 contain the entire chip-to-chip and off module signal wiring. Interconnections are made by vias 8. Power interconnection pins 9 are soldered to a card or board (not shown). Flexible carrier 2 extends beyond the sides of ceramic carrier 1, which may be provided with external connections. The advantages are as follows: - A low-cost ceramic carrier may be used. Only power distribution layers are required, so that the top surface has the most critical reference layer.

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Multi-Technology Chip Carrier

The chip carrier comprises a multilayer ceramic base carrier 1 on which a multilayer flexible polyimide carrier 2 is deposited. Chips 3 are connected to flexible carrier 2 by C4 connections 5. Ceramic carrier 1 comprises power distribution layers 6 (sandwich power plane structure). Conductive layers 7 of carrier 2 contain the entire chip-to-chip and off module signal wiring. Interconnections are made by vias 8. Power interconnection pins 9 are soldered to a card or board (not shown). Flexible carrier 2 extends beyond the sides of ceramic carrier 1, which may be provided with external connections. The advantages are as follows: - A low-cost ceramic carrier may be used. Only

power distribution layers are required, so that

the top surface has the most critical reference

layer.

- The power interconnection pin array on the ceramic

carrier is limited to a number that allows

soldering the pins to a card or board. Soldering

saves cost incurred by a connector and the

connection mechanism for very large arrays.

- The ceramic base ensures a thermal coefficient of

expansion which is compatible with that of the

chips. The ceramic material holds the polyimide

in place by power vias connecting the power planes

of the ceramic carrier to the chip.

- The chip-to-ceramic carrier power vias provide a

cooling path from the chip to the ceramic.

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