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CLOCK Generation With Single-Oscillator-Edge Control

IP.com Disclosure Number: IPCOM000039696D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Lewis, SD: AUTHOR [+2]

Abstract

In a clock signal generator circuit, the most critical timings are controlled by a single oscillator edge. The process variation effects are minimized because the critical clock generation timing block and the storage registers are on the same chip. (Image Omitted) Fig. 1 shows a typical level sensitive scan design (LSSD) where a Latch L1 is clocked by a CLOCK CI and a latch L2 is clocked by a CLOCK C2. Fig. 2 shows an on-chip clock generation network that produces a CLOCK C1 and CLOCK 2, as shown in Fig. 3. It is the task of block 600 in Fig. 2 to have a delay equal to Tc (clock overlap time), and hence to control the clock overlap. Tc must be less than the minimum delay through LATCH 20 and COMBINATORIAL LOGIC 22. The logic structure shown in Fig. 1 has four critical times that must be met to function properly. 1.

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CLOCK Generation With Single-Oscillator-Edge Control

In a clock signal generator circuit, the most critical timings are controlled by a single oscillator edge. The process variation effects are minimized because the critical clock generation timing block and the storage registers are on the same chip.

(Image Omitted)

Fig. 1 shows a typical level sensitive scan design (LSSD) where a Latch L1 is clocked by a CLOCK CI and a latch L2 is clocked by a CLOCK C2. Fig. 2 shows an on-chip clock generation network that produces a CLOCK C1 and CLOCK 2, as shown in Fig. 3. It is the task of block 600 in Fig. 2 to have a delay equal to Tc (clock overlap time), and hence to control the clock overlap. Tc must be less than the minimum delay through LATCH 20 and COMBINATORIAL LOGIC 22. The logic structure shown in Fig. 1 has four critical times that must be met to function properly. 1. The L2 to L2 clock cycle. 2. The L1 clock pulse width. 3. The L2 clock pulse width. 4. The L1 to L2 clock overlap. The L2 to L2 clock cycle is from CLOCK C2 rising edge to CLOCK C2 rising edge. The clock cycle is from the rise of PHASE X in the first cycle until the rise of the PHASE X in the second cycle, and thus, is single-edge controlled. The L1 and L2 clock pulse widths must exceed the minimum requirements of the technology. Since leading and trailing oscillator edges usually do not track well, their uncertainty must be added to the clock MPW (Minimum Pulse Width). The CLOCK C1 pulse width is a...