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Comparator to Detect Three or More Bits in Error in a Memory Word

IP.com Disclosure Number: IPCOM000039700D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Geneste, M: AUTHOR [+2]

Abstract

The data words stored into a memory may be in error due to a hardware failure of the memory cells. The failures in memory cells cause the bits which are read from these cells in error to be stuck at one or zero. Two bits in error are corrected by the memory error correction circuit, and the detection of three bits or more in error is to be reported to the device incorporating the memory. The logic shown in the Fig. 1 allows this operation to be performed. The word W which is read from a memory location is inverted. The inverted word is written into the same memory location and read. The word W' which is read is compared with W. The comparison allows a hardware failure to be detected. The words W and W' are provided to an XOR arrangement.

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Comparator to Detect Three or More Bits in Error in a Memory Word

The data words stored into a memory may be in error due to a hardware failure of the memory cells. The failures in memory cells cause the bits which are read from these cells in error to be stuck at one or zero. Two bits in error are corrected by the memory error correction circuit, and the detection of three bits or more in error is to be reported to the device incorporating the memory. The logic shown in the Fig. 1 allows this operation to be performed. The word W which is read from a memory location is inverted. The inverted word is written into the same memory location and read. The word W' which is read is compared with W. The comparison allows a hardware failure to be detected. The words W and W' are provided to an XOR arrangement. The outputs of the XOR arrangement are inverted, and all the bits of the R word which is so generated are at zero if no cell in the memory location is in error.

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If cells are in error (hard error), the bits of W' which are read from these cells have the same value as the corresponding bits of W. Thus, the word R contain one or several 1's. The presence of a number of bits at 1, equal or higher than three, is detected by the circuit shown in the drawing. Word R is split in groups of five bits. Assuming that the word locations in the memory contain 40 bits, the five bits A, B, C, D, and E of each group are provided to a first stage of logic arrangements LOG1-1 to LOG1-8. Each logic arrangement detects whether its five input bits are at 0, or one bit out of five is at 1, or two bits out of five is at 1 and g...