Browse Prior Art Database

Write Protection for a Non-Volatile RAM

IP.com Disclosure Number: IPCOM000039715D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Esteban, D: AUTHOR [+2]

Abstract

The up-to-date modems include a read access memory which stores the vital parameters defining the configuration in which the modem is used. When such a configuration is modified, the new parameters are written into the memory. In order to avoid the loss of the parameters at power off or under user control, the memory is made non-volatile (NV RAM) by use of a battery. Due to the risk of accidentally overwriting the data stored in the NV RAM, the write access sequence is made different from the read operation and valid for one write operation only. Referring to the figure, in which the address and data busses are not shown, the 02 decode selects a bank of N-position of the NV RAM, and the 01 decode is used to restore the Q1 Q2 latches. The processor must execute the following steps to write into the NV RAM: 1.

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Write Protection for a Non-Volatile RAM

The up-to-date modems include a read access memory which stores the vital parameters defining the configuration in which the modem is used. When such a configuration is modified, the new parameters are written into the memory. In order to avoid the loss of the parameters at power off or under user control, the memory is made non-volatile (NV RAM) by use of a battery. Due to the risk of accidentally overwriting the data stored in the NV RAM, the write access sequence is made different from the read operation and valid for one write operation only. Referring to the figure, in which the address and data busses are not shown, the 02 decode selects a bank of N-position of the NV RAM, and the 01 decode is used to restore the Q1 Q2 latches. The processor must execute the following steps to write into the NV RAM: 1. Reading of address 01 resulting in sending the signal "Chip select" (CS) 2. Reading of address 02 resulting in the transfer of write authorization into the first bistable Q1 at trailing edge of a first signal RD as a clock pulse 3. Reading of address 02 resulting in the transfer of write authorization into the second bistable Q2 at the trailing edge of a second signal RD as a clock pulse 4. Writing a byte into NV RAM when receiving signal WR 5. Reading of address 01 resulting in resetting "NV RAM write" The read access is performed in one read operation as for a standard RAM.

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