Browse Prior Art Database

HYBRID DIFFERENTIAL CASCODE CURRENT SWITCH SHIFT REGISTER LATCH

IP.com Disclosure Number: IPCOM000039716D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Bello, SE: AUTHOR [+4]

Abstract

The invention is a modified (hybrid) differential cascode current switch (DCCS) shift register latch (SRL) suitable for placement in a gate array environment in which emitter-coupled logic (ECL) elements from the basic logic cells for VLSI construction. The invention permits the DCCS SRL to interface directly with the ECL circuitry. ECL VLSI circuits are typically standardized in supply voltage to as small a value as possible to minimize power dissipation on the chip, while maintaining reliable operation. A problem encountered when "retrofitting" a DCCS SRL to that standardized environment is that the input signal voltages from the ECL logic elements are single ended, rather than differential, and thus can cause saturation of the transistors in the DCCS SRL array, impairing its operation.

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HYBRID DIFFERENTIAL CASCODE CURRENT SWITCH SHIFT REGISTER LATCH

The invention is a modified (hybrid) differential cascode current switch (DCCS) shift register latch (SRL) suitable for placement in a gate array environment in which emitter-coupled logic (ECL) elements from the basic logic cells for VLSI construction. The invention permits the DCCS SRL to interface directly with the ECL circuitry. ECL VLSI circuits are typically standardized in supply voltage to as small a value as possible to minimize power dissipation on the chip, while maintaining reliable operation. A problem encountered when "retrofitting" a DCCS SRL to that standardized environment is that the input signal voltages from the ECL logic elements are single ended, rather than differential, and thus can cause saturation of the transistors in the DCCS SRL array, impairing its operation. The present invention avoids this saturation problem.

(Image Omitted)

Fig. 1 shows the L1 stage of a hybrid DCCS SRL, while Fig. 2 shows the L2 stage of the hybrid DCCS SRL. Referring to Fig. 1, the latch is standard, except for resistors R1, R2, and R3. V+, V- and Vt are the supply voltages; Vr is a reference voltage; D1 is the input signal line from the ECL circuitry; SCAN is the scan data line; +A is the scan clock; +C1 is the data clock; and NCLK is a lie that does high if neither +a nor +C1 are high, thus serving to hold data in the latch. +L1 and -L1 are output lines to the L2 stage. Conventional DCCS SRLs have resistors where R2 and R3 appear, but have a current source where voltage swings. This current source is typically a transistor and resistor connected in series, with the base of the transistor connected to a reference voltage which sets the current. However, it is this...