Browse Prior Art Database

ROS Combined With LSSD SRL Circuit for Fast Logic Testing

IP.com Disclosure Number: IPCOM000039753D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Corr, JL: AUTHOR [+2]

Abstract

A method is described which eliminates loading and unloading level sensitive scan design (LSSD) shift register latches (SRL), allowing test results to be monitored instantly on a go/no go basis, minimizing test time and equipment needed to perform semiconductor logic testing. Normally, very large-scale integration (VLSI) logic testing is performed by applying bit patterns to primary inputs and outputs (I/Os) and serially clocking data through LSSD shift register latches. By incorporating read-only storage (ROS) bits at the input and output of each LSSD SRL for direct parallel loading of test data and the expected results needed for comparison, serial loading and unloading of LSSD scan chains is eliminated, resulting in a considerable saving of test time. Fig. 1 shows a block diagram of a generalized LSSD ROS circuit.

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ROS Combined With LSSD SRL Circuit for Fast Logic Testing

A method is described which eliminates loading and unloading level sensitive scan design (LSSD) shift register latches (SRL), allowing test results to be monitored instantly on a go/no go basis, minimizing test time and equipment needed to perform semiconductor logic testing. Normally, very large-scale integration (VLSI) logic testing is performed by applying bit patterns to primary inputs and outputs (I/Os) and serially clocking data through LSSD shift register latches. By incorporating read-only storage (ROS) bits at the input and output of each LSSD SRL for direct parallel loading of test data and the expected results needed for comparison, serial loading and unloading of LSSD scan chains is eliminated, resulting in a considerable saving of test time. Fig. 1 shows a block diagram of a generalized LSSD ROS circuit. ROS A and B are both 1 x N bits long. Stored data from ROS A is loaded into the SRL by bit select and clocking the selected ROS line. This puts the ROS data into L1 of the SRL. The A clock pulses perform the scan-in function, C clock is the system clock and B clock shifts the data from L1 to L2 to LN. ROS B contains the expected results of the test which are compared with the actual level of the SRL. A faulty product is indicated when the actual results differ from the expected results, bringing up the no go line. This technique can be extended to logically sense the output of multiple LSSD/ROS strings utilizing one I/O pin for all outputs. Because a VLSI logic chip...