Browse Prior Art Database

Load Programmable Off-Chip Driver

IP.com Disclosure Number: IPCOM000039755D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Erdelyi, CN: AUTHOR [+3]

Abstract

Load capacitance is programmed into off-chip drivers (OCDs) before or after a chip is designed and placed, such that proper drive is selected to minimize clock skew. Thus, a user may place an OCD of a single design at any point on a card and supply needed capability to drive to any other point on the card with proper timing. The arrival of a drive pulse having sufficient amplitude to switch the receiver can occur at varying time (known as clock skew), depending upon the load being driven by the OCD. By constructing an OCD such that appropriate power to drive into varying load capacitance can be programmed into it, clock skew is avoided and only a single OCD design is needed. The OCD is comprised of several circuit segments: a basic drive circuit designed to drive, e.g.

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Load Programmable Off-Chip Driver

Load capacitance is programmed into off-chip drivers (OCDs) before or after a chip is designed and placed, such that proper drive is selected to minimize clock skew. Thus, a user may place an OCD of a single design at any point on a card and supply needed capability to drive to any other point on the card with proper timing. The arrival of a drive pulse having sufficient amplitude to switch the receiver can occur at varying time (known as clock skew), depending upon the load being driven by the OCD. By constructing an OCD such that appropriate power to drive into varying load capacitance can be programmed into it, clock skew is avoided and only a single OCD design is needed. The OCD is comprised of several circuit segments: a basic drive circuit designed to drive, e.g., a 20pf load, and several additional segments having power to drive into a load, such as an additional 10pf. Additionally, the OCD is equipped with two latch cells which may be scanned in and programmed even after the chip is placed and wired. The data in the two latch cells is decoded to select the number of 10pf drive increments to be added to the basic driver. By input to the latch cells and decoding, as illustrated in the table below, 20pf, 30pf, 40pf, or 50pf of load may be driven. For example, with a 0 in both cell A and cell B, only the basic 20pf driver is on. With a 0 in cell A and a 1 in cell B, one additional circuit segment is also on, thus providing dr...