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High-Performance Microcode Command Architecture

IP.com Disclosure Number: IPCOM000039757D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Freeman, WA: AUTHOR [+2]

Abstract

A method is described to maximize the efficiency of the process of issuing commands to a processor. The design of an attachment adapter that contains a processor presents a number of design trade-offs concerning the ease of interfacing and adapter performance. This invention provides a means by which the majority of the adapter commands can be initiated as a result of a single I/O write operation. This technique removes the requirement that the system processor and the adapter processor be synchronized during the command initiation process. The addition of a processor to a device attachment adapter permits this adapter to provide an extremely flexible solution to a variety of device attachment problems.

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High-Performance Microcode Command Architecture

A method is described to maximize the efficiency of the process of issuing commands to a processor. The design of an attachment adapter that contains a processor presents a number of design trade-offs concerning the ease of interfacing and adapter performance. This invention provides a means by which the majority of the adapter commands can be initiated as a result of a single I/O write operation. This technique removes the requirement that the system processor and the adapter processor be synchronized during the command initiation process. The addition of a processor to a device attachment adapter permits this adapter to provide an extremely flexible solution to a variety of device attachment problems. In the IBM RT PC Multi-Protocol Communications Adapter, the adapter processor permits this adapter to provide a powerful, high performance solution to the problem of attachment to a variety of data communications devices and networks. Inherent with this variety is a problem of the complexity of the command interface that must be supported. In accordance with the new method, a 'three- tiered' command architecture and a single 8-bit command path is employed. The use of a single 8-bit command path permits initiation of adapter processor commands to be accomplished via a single I/O writer operation. This 8-bit command field must then be defined in such a way as to encompass all of the required adapter functions. In the case of the IBM RT PC Multi-Protocol Communications Adapter, a single 8-bit field was not sufficient to define all of the command and parameter options that are required to support a variety of data communications attachments. The tiered command architecture that provided a solution to this problem is described. Tier # 1: 'POR Mode' Adapter commands. This tier of adapter

commands is composed of a set of eight general-purpose adapter commands that are provided by the adapter's

read-only Storage (ROS). These commands provide a

native diagnostic capability and facilitate the

download and execution of adapter RAM resident

programming. Each 8-bit POR Mode adapter command

contains a 4-bit command identifier field and a 4-bit

parameter field per the following definition:

Tier # 2: 'Operating Mode' Adapter commands. This tier of

adapter commands is composed of a set of sixteen

adapter commands that are provided by the adapter's

downloaded RAM resident program. The process of

downloading the RAM resident program causes the

adapter processor to 'switch' to tier # 2 command

interpretation. These commands provide a set of

general data communications primitives that are

implemented by the RAM resident program. These

commands provide a nearly uniform command interface

for a device driver independent of the communications

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protocol being applied at the time. Differences in

command interpretation that are required due to

protocol differences are handled by the RAM...