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A Shorted-Path Diagnostic for the Physical Design of an Integrated Circuit Chip

IP.com Disclosure Number: IPCOM000039775D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Clark, K: AUTHOR [+2]

Abstract

During verification of the layout or physical design of a circuit, the determination of which wires undesirably short two or more schematic nets together can be performed with this method. Each contact in the single physical net is assigned to one of the schematic nets based upon its identifier. The shorted path is determined when a series of wires or shapes is found which links a contact or wire from one of the schematic nets to a contact or wire from a different schematic net. A short is defined as an error in the physical representation of a circuit such that two or more schematic nets are incorrectly represented in the physical implementation by just one physical net. Three steps are performed in the identification process for shorted nets. These steps are contact classification, path identification and path minimization.

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A Shorted-Path Diagnostic for the Physical Design of an Integrated Circuit Chip

During verification of the layout or physical design of a circuit, the determination of which wires undesirably short two or more schematic nets together can be performed with this method. Each contact in the single physical net is assigned to one of the schematic nets based upon its identifier. The shorted path is determined when a series of wires or shapes is found which links a contact or wire from one of the schematic nets to a contact or wire from a different schematic net. A short is defined as an error in the physical representation of a circuit such that two or more schematic nets are incorrectly represented in the physical implementation by just one physical net. Three steps are performed in the identification process for shorted nets. These steps are contact classification, path identification and path minimization. Fig. 1 shows a complete high-level representation of the shorted- path diagnostic with its three main steps highlighted. Fig. 2 shows a sample circuit schematic which has been implemented with the physical design shown in Fig. 3. Device contacts are shaded. In Fig. 3, the horizontal wire which connects the right side of R3 to the left side of R4 is in error and shorts schematic nets 1, 2 and 9 together. The entire shorted net is shown in Fig. 4. Each contact involved in the shorted net has some form of identifier associated with it, such as a name or an attribute of some form. In Fig. 3, Q1 and Q2 are transistors, which have contacts that are named PNP-COLL, PNP-BASE and PNP-EMIT. Q3 and Q4 are NPN transistors, which have contacts that are named NPN-COLL, NPN-BASE, and NPN-EMIT. All resistor contacts are named RES. PRES1, PRES2, PE1, PE2, PB and PM5V are uniquely named I/O connections. In Fig. 5, a mismatched nets list is derived by searching the lists of schematic and physical nets and discarding those nets which match from both lists. This will leave only the nets which do not match. Contacts of the mismatched physical net are checked for identifiers which are unique to just one of the schematic nets (Fig. 1, element 3). Identifiers which are not unique to one schematic net are discarded (Fig. 1, element 6), since a correct classification cannot be determined. In Fig. 5, the identifiers which are not unique are PNP-COLL and NPN-COLL, because they occur in two different schematic nets: 1 and 2. All unique identifiers are marked with the schematic net number associated with that unique identifier (Fig. 1, element 4). In Fig. 5, the only unique identifiers are NPN-BASE (schematic net...