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Table-Driven Hardware Controller

IP.com Disclosure Number: IPCOM000039777D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 54K

Publishing Venue

IBM

Related People

Sibbers, DE: AUTHOR [+2]

Abstract

A high-performance bus master is capable of automatically handling a plurality of concurrent operations on the bus. Simplicity and low cost are achieved by a unique control structure and the use of a RAM resident control table. Referring to Figs. 1-5, information from I/O devices attached via bus (21) is transferred into data area (60) of RAM (40). The low-level execution controls (20) provide high speed logic to communicate with I/O devices over bus (21). It also contains the logic to access RAM (40) and to allow microprogram (70) to access register stack (30). Use is made of data bus (23), Direct Memory Access Interface (22), Table Access Interface (24), and Register Access Interface (25).

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Table-Driven Hardware Controller

A high-performance bus master is capable of automatically handling a plurality of concurrent operations on the bus. Simplicity and low cost are achieved by a unique control structure and the use of a RAM resident control table. Referring to Figs. 1-5, information from I/O devices attached via bus (21) is transferred into data area
(60) of RAM (40). The low-level execution controls (20) provide high speed logic to communicate with I/O devices over bus (21). It also contains the logic to access RAM (40) and to allow microprogram (70) to access register stack (30). Use is made of data bus (23), Direct Memory Access Interface (22), Table Access Interface (24), and Register Access Interface (25). The Low Level Execution Controls (20) primarily performs primitive operations as directed by High Level Execution Controls (10) via Mini Command Interface (15) in Fig. 2). When a Mini-Command is received by the Mini Command Execution Controls (26) a busy signal is asserted until the Mini-Command completes. Use is made of control information in Register Stack (30) to obtain specific control information for the Mini-Command. Only three generic functions are performed as Mini-Commands: A. Polling operations on Bus (21) using Packet Transfer and Polling Controls (27). B. Packet transfers between Bus
(21) and Data Area (60) in RAM

(40) using Packet Transfer and Polling Controls (27) and DMA

Controls and FIFO Buffer (28). C. Transfers between Register Stack (38) and Table Area (50) in RAM (40) using Table and Register Access Controls (29). The High-Level Execution Controls (10) contains state machines which provide intelligence for autonomous operation. The state machines monitor service requests from Bus (21) and control registers in Register Stack (30). They then direct the Low-Level Execution Controls (20) to load appropriate control information from the Table Area (50) into Register Stack (30) and subsequently direct the Low-Level Execution Controls (20) to perform Bus functions specified by the control information loaded from Table Area (50). Communication between the High-Level Execution Controls (20) is via the Mini Command Interface (15). The control strategy used is based on the concept of multiple Execution Levels. Each Execution Level has a distinct generic control function which may be different from other Execution Levels. This characteristic allows a context switch of function in addition to the typical I/O device context switching.

As a result, simple state machines are able to implement complex control sequences that would normally be delegated to microcode. Each Execution Level has associated with it a hardware bit contained in Execution Level Mask Register (31) of Register Stack (30) to indicate if the Execution Level is active and a corresponding Execution Level Parameter (51) in Table Area (50) which defines the function of the level and which Slaves it applies to. Once the state machine senses a...