Browse Prior Art Database

Vertical Window CRT Address Generator

IP.com Disclosure Number: IPCOM000039783D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Parsons, DH: AUTHOR [+2]

Abstract

A technique is described whereby an address generator circuit refreshes cathode ray tube (CRT) display images during active display periods and transfers character font patterns to a buffer during vertical blanking intervals. The concept is an improvement over bit plane implementation in that it minimizes memory storage requirements and provides a means of expanding CRT vertical windows. A typical alphanumeric character generating display system, as shown in Fig. 1, consists of six key circuit blocks: Regen buffer 10, which contains the character and attribute code information, horizontal row scan counter 11, address generator 12, used to refresh the image; timing sequencer 13, character generator 14, used to store fonts, and pixel processing block 15.

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Vertical Window CRT Address Generator

A technique is described whereby an address generator circuit refreshes cathode ray tube (CRT) display images during active display periods and transfers character font patterns to a buffer during vertical blanking intervals. The concept is an improvement over bit plane implementation in that it minimizes memory storage requirements and provides a means of expanding CRT vertical windows. A typical alphanumeric character generating display system, as shown in Fig. 1, consists of six key circuit blocks: Regen buffer 10, which contains the character and attribute code information, horizontal row scan counter 11, address generator 12, used to refresh the image; timing sequencer 13, character generator 14, used to store fonts, and pixel processing block 15. The character code information is used to

(Image Omitted)

access the font pattern, both read and write, during character access cycles. The concept described herein improves on the operational functions of address generator 12. The technique used in this concept expands address generator 12, as shown in Fig. 2, by adding eight-bit register 16 and expanded multiplexer control block 17. Since the primary purpose of the address generator is to refresh the CRT image, an address is defined at start- of-screen register 18, incrementing every character row by the amount contained in logical line range register 19. By inserting eight-bit register 16 and expanded multiplexer control block 17 into the address generator circuitry, a unique new address creates a vertical window, whereby the next character row address is defined by eight-bit register 16. All subsequent...