Browse Prior Art Database

Direct Memory Access Enhancement

IP.com Disclosure Number: IPCOM000039792D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Krull, JW: AUTHOR [+6]

Abstract

A technique is described whereby the performance of direct memory access (DMA), as used in a storage control unit (SCU), is enhanced through the use of a DMA_Reserve line, in computer systems. The DMA_Reserve line expedites the handling of DMA operations by eliminating needless instruction fetch storage cycles. The computer system, as shown in Fig. 1, contains an SCU, a system bus adapter (SBA) and a processor bus (Pbus) for connection to the processors (PU). The SCU provides the interface to main storage for both the PU and the SBA. The SBA provides the interface between input/output (I/O) bus peripherals and main storage via the SCU. The processor bus (Pbus), and related control signals provide the means for communication between any two of the SCU, the PU and the SBA.

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Direct Memory Access Enhancement

A technique is described whereby the performance of direct memory access (DMA), as used in a storage control unit (SCU), is enhanced through the use of a DMA_Reserve line, in computer systems. The DMA_Reserve line expedites the handling of DMA operations by eliminating needless instruction fetch storage cycles. The computer system, as shown in Fig. 1, contains an SCU, a system bus adapter (SBA) and a processor bus (Pbus) for connection to the processors (PU). The SCU provides the interface to main storage for both the PU and the SBA. The SBA provides the interface between input/output (I/O) bus peripherals and main storage via the SCU. The processor bus (Pbus), and related control signals provide the means for communication between any two of the SCU, the PU and the SBA.

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Typically, the PU continually fetches instructions from the SCU. When the SBA performs a DMA (the process by which an I/O bus peripheral stores data in main storage via the SBA and the SCU), instruction fetching must stop so as to gain control of the SCU. The SCU cannot be a slave to both the SBA and the PU at the same time. Ideally, when the SBA receives data from a peripheral, it may gain control of the SCU and store the data without having to wait for an instruction fetch to be completed. In prior art, situations existed whereby cycle times were wasted, due to the fact that neither PU instruction fetches nor SBA data storages accurred. The technique described herein provides a means of eliminating wasted cycles and ensures that high priority DMA operations will take precedence over lower priority...