Browse Prior Art Database

Programmable Address Comparator

IP.com Disclosure Number: IPCOM000039798D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Wright, CG: AUTHOR

Abstract

An address comparator is described in which the size and location of the range to be recognized are programmable by external inputs. (Image Omitted) On any microprocessor bus, various devices attached to that bus must recognize certain addresses. In many systems, this address comparison is fixed in hardware. However, in some cases it is desirable to have this compare function programmable. This arrangement provides a variable compare function which can recognize a range of addresses whose size and location can both be altered. Fig. 1 illustrates the comparator, which consists of a number of single-bit comparators. These single-bit comparators compare incoming address against reference bits. Each of these is also fed with a signal which will force a true output, thus effectively disabling that particular compare.

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Programmable Address Comparator

An address comparator is described in which the size and location of the range to be recognized are programmable by external inputs.

(Image Omitted)

On any microprocessor bus, various devices attached to that bus must recognize certain addresses. In many systems, this address comparison is fixed in hardware. However, in some cases it is desirable to have this compare function programmable. This arrangement provides a variable compare function which can recognize a range of addresses whose size and location can both be altered. Fig. 1 illustrates the comparator, which consists of a number of single-bit comparators. These single-bit comparators compare incoming address against reference bits. Each of these is also fed with a signal which will force a true output, thus effectively disabling that particular compare. These 'compare disable' signals are decoded from a 'size' field, which determines how many of the upper address bits are used in the compare. Fig. 2 shows the function of the size decoder. As originally designed, this comparator is intended to be used on the upper eight bits of a 24-bit address. By looking at from 8 to 0 of the upper address bits, an address range of 64K to 16 megabytes, respectively, is recognized. The resulting comparator can be programmed to recognize any block of addresses of size 2N at any location which is a multiple of the block size
(i.e., a 256K block can be positioned at addresses 0, 256K, 512K, e...