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Dual-Current Sink for Digital-To-Analog Converter

IP.com Disclosure Number: IPCOM000039807D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Frankeny, RF: AUTHOR [+2]

Abstract

A high accuracy dual-current sink from a single output current sink digital-to-analog converter (DAC) is shown in the figure. The DAC module in the figure requires a current reference IREF . This current is generated by using an operational amplifier (op-amp) A3 buffer to a 1% zener diode 11. IREF = V2/R3 The output current Io = IREF x [Binary Digital Input] where all ones input = 2n-1 x IREF . 2n The head driver module for a printer has 2 chips, each which needs a digitally controlled current reference which is referenced to the rail voltage. Since the DAC has only 1 output Io, the circuit comprising components A1, A2, Q1, Q2, R1, R2 is used to generate IR1 and IR2 . R1 and R2 are in an R pac and their ratio is important but their absolute value is not.

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Dual-Current Sink for Digital-To-Analog Converter

A high accuracy dual-current sink from a single output current sink digital-to-analog converter (DAC) is shown in the figure. The DAC module in the figure requires a current reference IREF . This current is generated by using an operational amplifier (op-amp) A3 buffer to a 1% zener diode 11. IREF = V2/R3 The output current Io = IREF x [Binary Digital Input] where all ones input = 2n-1 x IREF . 2n The head driver module for a printer has 2 chips, each which needs a digitally controlled current reference which is referenced to the rail voltage. Since the DAC has only 1 output Io, the circuit comprising components A1, A2, Q1, Q2, R1, R2 is used to generate IR1 and IR2 . R1 and R2 are in an R pac and their ratio is important but their absolute value is not. Since op-amps A1 and A2 keep one end of R1 and R2 at ground and since the other end is common, the currents IE1 and IE2 are equal to Io/2, depending only on the ratio of R1 and R2 . Q1 and Q2 are Darlington transistors with minimum hfe > 500. Since IR1 is within .2% of IE1 and the same is true for IR2, the generation of these two current sinks is < 1% inaccuracy with respect to Io . A3 is required to buffer the zener reference voltage, and the op-amps can be an inexpensive quad package so A1 and A2 are essentially free. Transistors Q1 and Q2 transfer the currents to a voltage that can be as high as the breakdown of the collector base of Q1 and Q2 . Another feature...