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Prevention of Vertical Birds' Beaks During Oxidation of Semiconductor Structures

IP.com Disclosure Number: IPCOM000039811D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Beyer, KD: AUTHOR [+3]

Abstract

Disclosed is a method to avoid the formation of vertical birds' beaks along the sides of isolation trenches under the base region of semiconductor devices. This article suggests providing a source of silicon on top of the exposed trench liner to prevent oxidation of the epi region. During oxidation of some semiconductor structures, vertical birds' beaks are formed at the intersection of shallow and deep trenches. Additionally, during sidewall oxide removal by wet etching, a significant undercut of the thin thermal SiO2 layer covering the npn transistor area is possible. (Image Omitted) In the proposed process, after the formation of the shallow trench 1 (Fig. 1) by reactive ion etching (RIE) a layer of undoped polysilicon (PolySi) 2 is deposited.

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Prevention of Vertical Birds' Beaks During Oxidation of Semiconductor Structures

Disclosed is a method to avoid the formation of vertical birds' beaks along the sides of isolation trenches under the base region of semiconductor devices. This article suggests providing a source of silicon on top of the exposed trench liner to prevent oxidation of the epi region. During oxidation of some semiconductor structures, vertical birds' beaks are formed at the intersection of shallow and deep trenches. Additionally, during sidewall oxide removal by wet etching, a significant undercut of the thin thermal SiO2 layer covering the npn transistor area is possible.

(Image Omitted)

In the proposed process, after the formation of the shallow trench 1 (Fig. 1) by reactive ion etching (RIE) a layer of undoped polysilicon (PolySi) 2 is deposited. This covers a chemical vapor deposited (CVD) SiO2 layer 3, Si3N4 layer 4 and thermal SiO2 layer 5 The shallow trench overlaps the deep trench 6 which contains a silicon trench fill 7 topped by an oxide trench cap 8. A shallow trench sidewall 9 is next fabricated consisting of thermal SiO2 5A, CVD Si3N4 4A, and CVD SiO2 3A. The CVD SiO2 spacer 3 in the shallow trench is removed by wet etching in buffered HF and an oxide layer 10 (Fig. 2) is produced in the bottom of the shallow trench 1 by thermal oxidation of the undoped PolySi 2 (Fig. 1). If the length of the oxidation is adjusted so that only a small amount of the silicon 7, situated under...