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Logic Card Test Method

IP.com Disclosure Number: IPCOM000039814D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Ishii, T: AUTHOR [+3]

Abstract

This method relates to testing a logic card including a microprocessor. This method enables the detection of bugs in an unknown logic card easily and in a short time by using clock cycles of the microprocessor in comparing the operation of the logic card under test with that of a logic card which operates correctly. With reference to the figure, each of the pins of a logic card 2 which is to be tested is connected to one input of a corresponding exclusive-OR gate 6, and each of the pins of a logic card 4 which operates correctly is connected to the other input of the corresponding exclusive-OR gate 6. The number of exclusive-OR gates 6 is the same as the number of pins of the logic card 2 or 4.

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Logic Card Test Method

This method relates to testing a logic card including a microprocessor. This method enables the detection of bugs in an unknown logic card easily and in a short time by using clock cycles of the microprocessor in comparing the operation of the logic card under test with that of a logic card which operates correctly. With reference to the figure, each of the pins of a logic card 2 which is to be tested is connected to one input of a corresponding exclusive-OR gate 6, and each of the pins of a logic card 4 which operates correctly is connected to the other input of the corresponding exclusive-OR gate 6. The number of exclusive-OR gates 6 is the same as the number of pins of the logic card 2 or 4. An output of an oscillator 12 of the logic card 2 and an output of an oscillator 14 of the logic card 4 are connected together, and both of them are connected to an input of a counter 8. The counter 8 increments its contents in response to every cycle of the oscillator 12 or 14. Outputs of the counter 8 are connected to inputs of a register 10. When a logical "1" signal is applied to the control input of the register 10 from any one of the exclusive gates 6, the register 10 holds an output of the counter 8. In operation, the output of the oscillator 12 of the logic card to be tested is switched to a high-impedance state. Then, the output of the oscillator 14 of the logic card which operates correctly is used as a clock signal for the logic card 2 so that both the logic card 2 and 4 are synchronized. Nex...