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Process for Making Very Small, Asymmetric, Field-Effect Transistors

IP.com Disclosure Number: IPCOM000039819D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Nowak, EJ: AUTHOR

Abstract

A process is described for making field-effect transistors (FETs) having a lightly doped drain (LDD) and an abrupt junction at the source. Dimensions are smaller than current photo resolution allows by the use of sidewall techniques. Thus, very small, asymmetric LDD FETs are constructed having only 1/2 the resistance penalty of symmetric LDDs. Fig. 1 shows the results of first forming a series of film layers: a gate insulator 4, gate conductor (e.g., polysilicon) 6, and a mandrel-forming material 8 on silicon wafer 2. Next, an edge is formed in material 8 by photoetching. A conformal layer 10 is deposited over the surface and reactive ion etching (RIE) is used to remove the conformal layer from all planar surfaces, leaving only a sidewall coating of film 10, as shown.

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Process for Making Very Small, Asymmetric, Field-Effect Transistors

A process is described for making field-effect transistors (FETs) having a lightly doped drain (LDD) and an abrupt junction at the source. Dimensions are smaller than current photo resolution allows by the use of sidewall techniques. Thus, very small, asymmetric LDD FETs are constructed having only 1/2 the resistance penalty of symmetric LDDs. Fig. 1 shows the results of first forming a series of film layers: a gate insulator 4, gate conductor (e.g., polysilicon) 6, and a mandrel-forming material 8 on silicon wafer 2. Next, an edge is formed in material 8 by photoetching. A conformal layer 10 is deposited over the surface and reactive ion etching (RIE) is used to remove the conformal layer from all planar surfaces, leaving only a sidewall coating of film 10, as shown. Selective RIE removal of polysilicon 6 is next performed. A final step in coming to the condition shown in Fig. 1 is heavily doping source 12 by ion implantation followed by a drive-in anneal. To reach the condition shown in Fig. 2, mandrel material 8 is removed and polysilicon film 6 is selectively removed by RIE, thus forming gate electrode 6 having width W equivalent to the thickness of conformal material 10 as originally deposited. To complete the cross- section shown in Fig. 2, a very thin layer of silicon dioxide (SiO2) 14 is conformally deposited and light doping is performed by ion implantation. Thus, lightly doped region 16...