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Bit Slice Array Macro Concepts for Embedded Arrays

IP.com Disclosure Number: IPCOM000039829D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Enright, KY: AUTHOR [+3]

Abstract

Automatic design system rules coding work can be reduced by using bit slice techniques in the design of storage arrays. In the design of, for example, 32 x 9 and 32 x 36 storage array configurations, each configuration would have a set of physical design rules. For future configuration arrays, there will be another set of physical design rules to be coded and evaluated. Described is a method that uses the concept of bit slice array macro instead of RAM (ramdom-access memory) macro.

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Bit Slice Array Macro Concepts for Embedded Arrays

Automatic design system rules coding work can be reduced by using bit slice techniques in the design of storage arrays. In the design of, for example, 32 x 9 and 32 x 36 storage array configurations, each configuration would have a set of physical design rules. For future configuration arrays, there will be another set of physical design rules to be coded and evaluated. Described is a method that uses the concept of bit slice array macro instead of RAM (ramdom-access memory) macro. There could be, for example, five basic bit slice array macros: (l) 16 x 1 (2 read, 2 write) (2) 16 x 2 (1 read, 1 write)

(3) 32 x 1 (2 read, 2 write)

(4) 32 x 2 (1 read, 1 write)

(5) 64 x 1 (1 read, 1 write) In addition, there would be five basic stitched array elements: (a) 16 x 1 (2 read, 2 write) (b) 16 x 2 (1 read, 1 write)

(c) 32 x 1 (2 read, 2 write)

(d) 32 x 2 (1 read, 1 write)

(e) 64 x 1 (1 read, 1 write) Step 1. Treat all bit slice array macros and stitched array elements as logic macro books. Step 2. Define all technology rules for these ten "logic" books, and logic models for test generation. Step 3. Implement these technology rules in automatic design rules. Step 4. Any user then can implement his/her array configuration by using normal 'logic' book design methodology. For example, an array of 16 x 9 configuration can be implemented by using one-bit slice array macro 16 x 1 (2 read, 2 write) plus eight stitched elements 16...