Browse Prior Art Database

Interface Protocol for Attachment of BUS Units Having Limited I/O Pins to Processors Utilizing Several Buses

IP.com Disclosure Number: IPCOM000039835D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 5 page(s) / 51K

Publishing Venue

IBM

Related People

Float, GD: AUTHOR [+4]

Abstract

A requirement that every bus unit in a system be attached to all processor busses may cause the system layout to be repartitioned due to the limited number of inputs/outputs available on a card or on logic chips. This could result in the need for additional cards or chips to be installed and, in the process, limit the number of feature cards that could be used. This interface scheme allows a bus unit with limited I/O pins, either on the card or the logic chips, to be logically attached to a processor having several busses which transfer data on a single system cycle in the following manner. (Image Omitted) The scheme allows one or more Bus Units with limited I/O pins, i.e., a Slave Bus Unit (SBU), to be attached to a processor via a Bus Unit, which does have total bus interface with the processor, i.e.

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Interface Protocol for Attachment of BUS Units Having Limited I/O Pins to Processors Utilizing Several Buses

A requirement that every bus unit in a system be attached to all processor busses may cause the system layout to be repartitioned due to the limited number of inputs/outputs available on a card or on logic chips. This could result in the need for additional cards or chips to be installed and, in the process, limit the number of feature cards that could be used. This interface scheme allows a bus unit with limited I/O pins, either on the card or the logic chips, to be logically attached to a processor having several busses which transfer data on a single system cycle in the following manner.

(Image Omitted)

The scheme allows one or more Bus

Units with limited I/O pins, i.e., a Slave Bus Unit (SBU), to be attached to a processor via a Bus Unit, which does have total bus interface with the processor, i.e., a Master Bus Unit (MBU). The MBU and SBU must have a shared common bus on which data transfers may take place. In addition, the MBU must add two registers and three control lines. Several SBUs may use this interface; however, additional control lines would be required to insure that only one SBU was responding to the Processing Unit (PU) and the arbiter at any one time. Fig. 1 shows the layout of the interface. Each Bus Unit must have connection to the PU control lines and the command bus.

(Image Omitted)

There are four different types of

Processor Bus Operations (PBOs) handled by this interface. 1. Load Only An address field and data field is

sent to a

Bus Unit from the PU.

2. Copy Only A data field is sent from a Bus

Unit back to

the PU. 3. Load and Copy An address and data field is transferred to a Bus Unit with a return data field sent back in

the same operation.

(Image Omitted)

4. Load and This is similar to the load and copy except Delayed Copy the time required to gather the data requested

takes several cycles.

Load Only Description uses the timing diagram in Fig.

2 and has the following sequence:

1

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1. The PU sends out PBO Request at T2 of cycle 1

minus 1 and gates the address bus and data bus

from T0 to T0 of cycle 1.

2. The Bus Unit, seeing PBO Request active, clocks

the command at T0 of cycle 1.

(Image Omitted)

3. The Bus Unit decoding the operation responds at T1

of cycle 1 with Unit Busy. Because this example

assumes the Slave Bus Unit is the responding Bus

Unit, both Freeze PBO Buffer and Bus Unit PBO

Request are also activated at T1 of cycle 1.

4. The Master Bus Unit receives Freeze PBO Buffer at

TL which prevents further clocking of the A-Reg

and D-Reg data.

5. The arbiter receives the Bus Unit PBO Request for

the bus at T0 of cycle 2 and, if the bus is free,

responds at T1 of cycle 2 with PBO Grant. 6. Receipt of PBO Grant by both the MBU and SBU at TL of cycle 2 signals the MBU to transfer the

A-Reg data from T0 of cycle 3 to T0 of cycle 4.

The SBU will clock this data at T2 of cycle 3 into

its A...