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Receiver Circuit for Pulsed External Inputs

IP.com Disclosure Number: IPCOM000039839D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

The off-chip receiver circuit, shown in Fig. 1, offers many advantages over conventional circuit approaches by allowing external chip-to-chip signal lines to be pulsed rather than to be held at constant levels. Among the performance gains realizable by pulsed inputs are reductions in system power, lowered WT, faster operation and greater immunity to ringing on the line. These improvements are achieved by normally keeping the off-chip line at a level halfway between the up level and the down level. To transmit information, a pulse is placed on the off-chip data line, momentarily driving it to the full logic level, as illustrated in Fig. 2. Any push-pull driver with output inhibit can be used to generate this off-chip signal, with appropriate clocking, a concept (Image Omitted) shown in Fig. 3.

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Receiver Circuit for Pulsed External Inputs

The off-chip receiver circuit, shown in Fig. 1, offers many advantages over conventional circuit approaches by allowing external chip-to-chip signal lines to be pulsed rather than to be held at constant levels. Among the performance gains realizable by pulsed inputs are reductions in system power, lowered WT, faster operation and greater immunity to ringing on the line. These improvements are achieved by normally keeping the off-chip line at a level halfway between the up level and the down level. To transmit information, a pulse is placed on the off-chip data line, momentarily driving it to the full logic level, as illustrated in Fig. 2. Any push-pull driver with output inhibit can be used to generate this off-chip signal, with appropriate clocking, a concept

(Image Omitted)

shown in Fig. 3. The termination resistors can be set so the external net is kept halfway between the up level and the down level when all drivers are inhibited. The driver is then uninhibited whenever a data pulse is to be sent. The circuit, shown in Fig. 1, implements a receiver for this off- chip signal by the following means. Transistor T1 acts as both a level sensor for the logic low level and as part of a latch formed by transistors T1 and T2 . When the external input is low, transistor T1 is guaranteed to be off. This causes the voltage of the output node to rise, thus turning transistor T2 on, which pulls the base of transistor T1 low, thereby guaranteeing that the output will remain high. On the other hand, if the external input is high, diode D1 effectively disconnects the external input from the base of transistor T1 . Under this condition, the base voltage of T1 is set by the collector voltage of transistor T2 . If T2 is conducting, the case is the same as outlined previously. If...