Browse Prior Art Database

Minimized Parity Predict Circuit for Incrementation

IP.com Disclosure Number: IPCOM000039847D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Kalla, R: AUTHOR

Abstract

Maintaining parity on a byte of information after it has been incremented is typically accomplished by regeneration after the increment is performed. This causes the parity bit to be slower than the incrementation output and the increment is not checked for the correct output. Some designs use look-ahead functions on the carry bits of the increment. This solves the timing problem but requires more circuitry. A new circuit efficiently predicts parity using minimal hardware, as described below. The circuit, seen in the drawing, will predict either even or odd parity on an eight-bit wraparound incrementer. This uses an exclusive OR methodology and is a realization of the following boolean equation:

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Minimized Parity Predict Circuit for Incrementation

Maintaining parity on a byte of information after it has been incremented is typically accomplished by regeneration after the increment is performed. This causes the parity bit to be slower than the incrementation output and the increment is not checked for the correct output. Some designs use look-ahead functions on the carry bits of the increment. This solves the timing problem but requires more circuitry. A new circuit efficiently predicts parity using minimal hardware, as described below. The circuit, seen in the drawing, will predict either even or odd parity on an eight-bit wraparound incrementer. This uses an exclusive OR methodology and is a realization of the following boolean equation:

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