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Pseudo Three-Port Instruction Buffer

IP.com Disclosure Number: IPCOM000039855D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Dulzo, JJ: AUTHOR [+2]

Abstract

The instruction storage unit (ISU) of the IBM 9375 Series machine has a need for two distinct functions: (1) an eight-word instruction buffer function which improves system efficiency by allowing the ISU to pass instructions to the instruction processing unit (IPU) during cache line loads, and (2) a one-word data register function which latches and holds instructions to provide proper write timing to the cache array, also during cache line loads. A structure which uses common logic to implement both of the above functions results in a significant reduction of logic cells, as described below. (Image Omitted) This instruction buffer/data register logic is unique because the 8th (last) buffer register serves two purposes. It handles the normal 8th register instruction buffer function, and it handles the data register function.

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Pseudo Three-Port Instruction Buffer

The instruction storage unit (ISU) of the IBM 9375 Series machine has a need for two distinct functions: (1) an eight-word instruction buffer function which improves system efficiency by allowing the ISU to pass instructions to the instruction processing unit (IPU) during cache line loads, and (2) a one-word data register function which latches and holds instructions to provide proper write timing to the cache array, also during cache line loads. A structure which uses common logic to implement both of the above functions results in a significant reduction of logic cells, as described below.

(Image Omitted)

This instruction buffer/data register logic is unique because the 8th (last) buffer register serves two purposes. It handles the normal 8th register instruction buffer function, and it handles the data register function. Overall, this results in a pseudo three-port array function with one input and two outputs, where one of the two outputs has a limited (specific) function. In order to understand the advantages of the pseudo three-port implementation of the instruction buffer/data register, it is helpful to first understand the basic requirements placed on this logic and the logic structure when the buffer and data register are implemented separately. Initially ignoring the specific implementation, the required logic function is as follows: A. Store all eight instructions received from storage

(one per machine cycle) during one cache line

load.

(Image Omitted)

B. Pass instructions sequentially from the buffer to

the instruction bus when required by machine

conditions. (Note: there are conditions which

cause the read operation to pause while the write

operation continues. This necessitates the

storing of all eight words so that the reads can

be independent of the writes.)

C. Latch the latest instruction received from storage

for one cycle to provide the correct data input

timing for the cache array. Figs. 1a and 1b show the structure and timing of the instruction buffer and data register when they are implemented separately, using nine 36-bit registers. Fig. 1a shows how the logic requirements are satisfied. The storage bus has paths into all eight buffer registers which allow all eight instructions to be latched from storage. There are paths from each register output which allow instructions to be placed on the instruction bus via the multiplexer, and the data register has the paths necessary to latch the latest instruction from storage and hold

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it for input to the cache array.

(Image Omitted)

Fig. 1b shows the timing of the write and read ope...